SBASAM0A
March 2024 – June 2024
ADS127L18
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements
5.7
Switching Characteristics
5.8
Timing Diagrams
6
Parameter Measurement Information
6.1
Offset Error Measurement
6.2
Offset Drift Measurement
6.3
Gain Error Measurement
6.4
Gain Drift Measurement
6.5
NMRR Measurement
6.6
CMRR Measurement
6.7
PSRR Measurement
6.8
SNR Measurement
6.9
INL Error Measurement
6.10
THD Measurement
6.11
IMD Measurement
6.12
SFDR Measurement
6.13
Noise Performance
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Analog Inputs (AINP, AINN)
7.3.1.1
Input Range
7.3.2
Reference Voltage (REFP, REFN)
7.3.2.1
Reference Voltage Range
7.3.3
Clock Operation
7.3.3.1
Internal Oscillator
7.3.3.2
External Clock
7.3.4
Power Supplies
7.3.4.1
AVDD1 and AVSS
7.3.4.2
AVDD2
7.3.4.3
IOVDD
7.3.4.4
Power-On Reset (POR)
7.3.4.5
CAPA and CAPD
7.3.5
VCM Output Voltage
7.3.6
GPIO
7.3.7
Modulator
7.3.8
Digital Filter
7.3.8.1
Wideband Filter
7.3.9
Low-Latency Filter (Sinc)
7.3.9.1
Sinc4 Filter
7.3.9.2
Sinc4 + Sinc1 Cascade Filter
7.3.9.3
Sinc3 Filter
7.3.9.4
Sinc3 + Sinc1 Filter
7.4
Device Functional Modes
7.4.1
Speed Modes
7.4.2
Synchronization
7.4.2.1
Synchronized Control Mode
7.4.2.2
Start/Stop Control Mode
7.4.3
Digital Filter Settling
7.4.4
Conversion-Start Delay Time
7.4.5
Data Averaging
7.4.6
Calibration
7.4.6.1
Offset Calibration Registers
7.4.6.2
Gain Calibration Registers
7.4.6.3
Calibration Procedure
7.4.7
Reset
7.4.7.1
RESET Pin
7.4.7.2
Reset by SPI Register
7.4.7.3
Reset by SPI Input Pattern
7.4.8
Power-Down
7.4.9
Idle and Standby Modes
7.4.10
Diagnostics
7.4.10.1
ERROR Pin and ERR_FLAG Bit
7.4.10.2
Clock Counter
7.4.10.3
SCLK Counter
7.4.10.4
Frame-Sync CRC
7.4.10.5
SPI CRC
7.4.10.6
Register Map CRC
7.4.10.7
Self Test
7.4.11
Frame-Sync Data Port
7.4.11.1
FSYNC Pin
7.4.11.2
DCLK Pin
7.4.11.3
DOUT Pins
7.4.11.4
DIN Pins
7.4.11.5
Time Division Multiplexing
7.4.11.6
Daisy Chain
7.4.11.7
Data Packet
7.4.11.8
STATUS_DP Header
7.4.11.9
Data Port Timing Adjustment
7.5
Programming
7.5.1
Hardware Programming
7.5.2
SPI Programming
7.5.2.1
Chip Select (CS)
7.5.2.2
Serial Clock (SCLK)
7.5.2.3
Serial Data Input (SDI)
7.5.2.4
Serial Data Output (SDO)
7.5.3
SPI Frame
7.5.4
SPI Commands
7.5.4.1
Read Register Command
7.5.4.2
Write Register Command
7.5.5
SPI Daisy-Chain
8
Register Map
9
Application and Implementation
9.1
Application Information
9.1.1
Input Driver
9.1.2
Antialias Filter
9.1.3
Reference Voltage
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
12.1
Mechanical Data
6
Parameter Measurement Information