SBASAM0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
The offset calibration value is a 24-bit word consisting of three 8-bit registers coded in two's-complement format. The offset value is subtracted from the conversion data. The ordering of the three-byte offset value is the low address for the most-significant byte. See the CHn Offset register for the offset register addresses of each channel. If the ADC is programmed for 16-bit data mode, the data are left-justified to the most-significant offset byte. This justification enables sub-LSB offset capability in 16-bit data mode. Table 7-11 shows example offset calibration values.
OFFSET REGISTER VALUE | OFFSET APPLIED |
---|---|
000010h | –16LSB |
000001h | –1LSB |
FFFFFFh | 1LSB |
FFFFF0h | 16LSB |