SBASAM0B March   2024  – November 2024 ADS127L18

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Clock Dividers
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 External Clock
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
        2. 7.3.8.2 Low-Latency Filter (Sinc)
          1. 7.3.8.2.1 Sinc4 Filter
          2. 7.3.8.2.2 Sinc4 + Sinc1 Cascade Filter
          3. 7.3.8.2.3 Sinc3 Filter
          4. 7.3.8.2.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Reset
        1. 7.4.1.1 RESET Pin
        2. 7.4.1.2 Reset by SPI Register
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2  Idle and Standby Modes
      3. 7.4.3  Power-Down
      4. 7.4.4  Speed Modes
      5. 7.4.5  Synchronization
        1. 7.4.5.1 Synchronized Control Mode
        2. 7.4.5.2 Start/Stop Control Mode
      6. 7.4.6  Conversion-Start Delay Time
      7. 7.4.7  Calibration
        1. 7.4.7.1 Offset Calibration Registers
        2. 7.4.7.2 Gain Calibration Registers
        3. 7.4.7.3 Calibration Procedure
      8. 7.4.8  Data Averaging
      9. 7.4.9  Diagnostics
        1. 7.4.9.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.9.2 SPI CRC
        3. 7.4.9.3 Register Map CRC
        4. 7.4.9.4 ADC Error
        5. 7.4.9.5 SPI Address Range
        6. 7.4.9.6 SCLK Counter
        7. 7.4.9.7 Clock Counter
        8. 7.4.9.8 Frame-Sync CRC
        9. 7.4.9.9 Self Test
      10. 7.4.10 Frame-Sync Data Port
        1. 7.4.10.1  Data Packet
        2. 7.4.10.2  Data Format
        3. 7.4.10.3  STATUS_DP Header Byte
        4. 7.4.10.4  FSYNC Pin
        5. 7.4.10.5  DCLK Pin
        6. 7.4.10.6  DOUTx Pins
        7. 7.4.10.7  DINx Pins
        8. 7.4.10.8  Time Division Multiplexing
        9. 7.4.10.9  Daisy Chain
        10. 7.4.10.10 DOUTx Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 Commands
        1. 7.5.4.1 Write Register Command
        2. 7.5.4.2 Read Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 AVDD1 and AVSS
      2. 9.3.2 AVDD2
      3. 9.3.3 IOVDD
      4. 9.3.4 CAPA and CAPD
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8 Register Map

Table 8-1 lists the register memory map of the ADS127L14 and ADS127L18. Memory addresses 02h to 10h are common programming to all device channels. Addresses 11h through 30h apply to device channels 0 through 3. Addresses 31h through 50h apply to device channels 4 through 7. Unlisted register addresses are not to be written to.

Table 8-1 Register Map Summary
Address Register Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00h DEV_ID xxh DEV_ID[7:0]
01h REV_ID xxh REV_ID[7:0]
02h STATUS 60h RESERVED ALV_FLAG POR_FLAG SPI_ERR REG_ERR ADC_ERR ADDR_ERR SCLK_ERR
03h CLK_CNT 00h CLK_CNT[7:0]
04h GPIO_RD 00h GPIO_RD[7:0]
05h CRC_MSB 00h CRC_MSB[7:0]
06h CRC_LSB 00h CRC_LSB[7:0]
07h CONTROL 00h RESET[5:0] START STOP
08h GEN_CFG1 00h RESERVED DELAY[2:0] VCM REFP_BUF REF_RNG
09h GEN_CFG2 04h AVG_MODE[1:0] RESERVED START_MODE[1:0] SPEED_MODE[1:0] STBY_MODE
0Ah GEN_CFG3 80h OUT_DRV DATA CLK_CNT_EN SPI_STAT_EN SPI_ADDR_EN SCLK_CNT_EN SPI_CRC_EN REG_CRC_EN
0Bh DP_CFG1 20h DP_CRC_EN DP_STAT_EN DP_TDM[1:0] RESERVED DP_DAISY RESERVED
0Ch DP_CFG2 00h RESERVED DCLK_DIV[1:0] DOUT_DLY[4:0]
0Dh CLK_CFG 00h RESERVED CLK_SEL CLK_DIV[2:0]
0Eh GPIO_WR 00h GPIO_WR[7:0]
0Fh GPIO_DIR 00h GPIO_DIR[7:0]
10h GPIO_EN 00h GPIO_EN[7:0]
11h CH0_CFG1 00h RESERVED CH0_MUX[2:0] CH0_INP_RNG CH0_EX_RNG CH0_BUFN CH0_BUFP
12h CH0_CFG2 00h RESERVED CH0_PWDN CH0_FLTR[4:0]
13h CH0_OFS_MSB 00h CH0_OFFSET_MSB[7:0]
14h CH0_OFS_MID 00h CH0_OFFSET_MID[7:0]
15h CH0_OFS_LSB 00h CH0_OFFSET_LSB[7:0]
16h CH0_GAN_MSB 40h CH0_GAIN_MSB[7:0]
17h CH0_GAN_MID 00h CH0_GAIN_MID[7:0]
18h CH0_GAN_LSB 00h CH0_GAIN_LSB[7:0]
19h CH1_CFG1 00h RESERVED CH1_MUX[2:0] CH1_INP_RNG CH1_EX_RNG CH1_BUFN CH1_BUFP
1Ah CH1_CFG2 00h RESERVED CH1_PWDN CH1_FLTR[4:0]
1Bh CH1_OFS_MSB 00h CH1_OFFSET_MSB[7:0]
1Ch CH1_OFS_MID 00h CH1_OFFSET_MID[7:0]
1Dh CH1_OFS_LSB 00h CH1_OFFSET_LSB[7:0]
1Eh CH1_GAN_MSB 40h CH1_GAIN_MSB[7:0]
1Fh CH1_GAN_MID 00h CH1_GAIN_MID[7:0]
20h CH1_GAN_LSB 00h CH1_GAIN_LSB[7:0]
21h CH2_CFG1 00h RESERVED CH2_MUX[2:0] CH2_INP_RNG CH2_EX_RNG CH2_BUFN CH2_BUFP
22h CH2_CFG2 00h RESERVED CH2_PWDN CH2_FLTR[4:0]
23h CH2_OFS_MSB 00h CH2_OFFSET_MSB[7:0]
24h CH0_OFS_MID 00h CH2_OFFSET_MID[7:0]
25h CH2_OFS_LSB 00h CH2_OFFSET_LSB[7:0]
26h CH2_GAN_MSB 40h CH2_GAIN_MSB[7:0]
27h CH2_GAN_MID 00h CH2_GAIN_MID[7:0]
28h CH2_GAN_LSB 00h CH2_GAIN_LSB[7:0]
29h CH3_CFG1 00h RESERVED CH3_MUX[2:0] CH3_INP_RNG CH3_EX_RNG CH3_BUFN CH3_BUFP
2Ah CH3_CFG2 00h RESERVED CH3_PWDN CH3_FLTR[4:0]
2Bh CH3_OFS_MSB 00h CH3_OFFSET_MSB[7:0]
2Ch CH3_OFS_MID 00h CH3_OFFSET_MID[7:0]
2Dh CH3_OFS_LSB 00h CH3_OFFSET_LSB[7:0]
2Eh CH3_GAN_MSB 40h CH3_GAIN_MSB[7:0]
2Fh CH3_GAN_MID 00h CH3_GAIN_MID[7:0]
30h CH3_GAN_LSB 00h CH3_GAIN_LSB[7:0]
31h CH4_CFG1 00h RESERVED CH4_MUX[2:0] CH4_INP_RNG CH4_EX_RNG CH4_BUFN CH4_BUFP
32h CH4_CFG2 00h RESERVED CH4_PWDN CH4_FLTR[4:0]
33h CH4_OFS_MSB 00h CH4_OFFSET_MSB[7:0]
34h CH4_OFS_MID 00h CH4_OFFSET_MID[7:0]
35h CH4_OFS_LSB 00h CH4_OFFSET_LSB[7:0]
36h CH4_GAN_MSB 40h CH4_GAIN_MSB[7:0]
37h CH4_GAN_MID 00h CH4_GAIN_MID[7:0]
38h CH4_GAN_LSB 00h CH4_GAIN_LSB[7:0]
39h CH5_CFG1 00h RESERVED CH5_MUX[2:0] CH5_INP_RNG CH5_EX_RNG CH5_BUFN CH5_BUFP
3Ah CH5_CFG2 00h RESERVED CH5_PWDN CH5_FLTR[4:0]
3Bh CH5_OFS_MSB 00h CH5_OFFSET_MSB[7:0]
3Ch CH5_OFS_MID 00h CH5_OFFSET_MID[7:0]
3Dh CH5_OFS_LSB 00h CH5_OFFSET_LSB[7:0]
3Eh CH5_GAN_MSB 40h CH5_GAIN_MSB[7:0]
3Fh CH5_GAN_MID 00h CH5_GAIN_MID[7:0]
40h CH5_GAN_LSB 00h CH5_GAIN_LSB[7:0]
41h CH6_CFG1 00h RESERVED CH6_MUX[2:0] CH6_INP_RNG CH6_EX_RNG CH6_BUFN CH6_BUFP
42h CH6_CFG2 00h RESERVED CH6_PWDN CH6_FLTR[4:0]
43h CH6_OFS_MSB 00h CH6_OFFSET_MSB[7:0]
44h CH6_OFS_MID 00h CH6_OFFSET_MID[7:0]
45h CH6_OFS_LSB 00h CH6_OFFSET_LSB[7:0]
46h CH6_GAN_MSB 40h CH6_GAIN_MSB[7:0]
47h CH6_GAN_MID 00h CH6_GAIN_MID[7:0]
48h CH6_GAN_LSB 00h CH6_GAIN_LSB[7:0]
49h CH7_CFG1 00h RESERVED CH7_MUX[2:0] CH7_INP_RNG CH7_EX_RNG CH7_BUFN CH7_BUFP
4Ah CH7_CFG2 00h RESERVED CH7_PWDN CH7_FLTR[4:0]
4Bh CH7_OFS_MSB 00h CH7_OFFSET_MSB[7:0]
4Ch CH7_OFS_MID 00h CH7_OFFSET_MID[7:0]
4Dh CH7_OFS_LSB 00h CH7_OFFSET_LSB[7:0]
4Eh CH7_GAN_MSB 40h CH7_GAIN_MSB[7:0]
4Fh CH7_GAN_MID 00h CH7_GAIN_MID[7:0]
50h CH7_GAN_LSB 00h CH7_GAIN_LSB[7:0]

Table 8-2 shows the access-type codes in this section.

Table 8-2 Register Access-Type Codes
Access Type Code Description
R R Read only
W W Write only
W1C W1C Write 1 to clear
R/W R/W Read or write

8.1 DEV_ID Register (Address = 00h) [Reset = 04h or 06h]

DEV_ID is described in Table 8-3.

Table 8-3 DEV_ID Register Description
Bit Field Type Reset Description
7-0 DEV_ID[7:0] R 00000xx0b Device identification number.
00000100b = ADS127L14
00000110b = ADS127L18

8.2 REV_ID Register (Address = 01h) [Reset = xxh]

REV_ID is described in Table 8-4.

Table 8-4 REV_ID Register Description
Bit Field Type Reset Description
7-0 REV_ID[7:0] R xxxxxxxxb Die revision number.
The die revision number is subject to change during device production without prior notice.

8.3 STATUS Register (Address = 02h) [Reset = 60h]

STATUS is shown in Figure 8-51 and described in Table 8-24.

Figure 8-1 STATUS Register
7 6 5 4 3 2 1 0
RESERVED ALV_FLAG POR_FLAG SPI_ERR REG_ERR ADC_ERR ADDR_ERR SCLK_ERR
R-0b R/W1C-1b R/W1C-1b R/W1C-0b R/W1C-0b R-0b R/W1C-0b R/W1C-0b
Table 8-5 STATUS Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0b Reserved
6 ALV_FLAG R/W1C 1b Analog supply low-voltage flag.
This bit indicates a low-voltage condition of the analog power supplies. Write 1b to reset the flag to detect the next occurrence of a low-voltage condition.
0b = No event from when flag last cleared
1b = Analog power supply low-voltage detected
5 POR_FLAG R/W1C 1b Power-on reset flag.
This bit indicates the device was reset at power-on or brownout of the IOVDD power supply or by a user reset operation. Write 1b to reset the flag to detect the next occurrence of a device reset.
0b = No reset from when flag last cleared
1b = Reset occurred
4 SPI_ERR R/W1C 0b SPI CRC error.
This bit indicates an SPI CRC error was detected. Except for this register, register write operations are blocked when the bit is set. Clear the bit by writing 1b. CRC validation is enabled by the SPI_CRC_EN bit.
0b = No error
1b = SPI CRC error
3 REG_ERR R/W1C 0b Register map CRC error.
This bit indicates a register map CRC error. The user writes a 16-bit CRC value to the CRC_MSB and CRC_LSB registers, calculated over addresses 08h to 50h for both devices. Clear the error by correcting the CRC value, then write 1b to clear the bit. The register map CRC validation is enabled by the REG_CRC_EN register bit.
0b = No error
1b = Register map CRC error
2 ADC_ERR R 0b ADC error.
This bit indicates an internal ADC error. Reset the device or perform a power cycle to clear the error.
0b = No error
1b = ADC error
1 ADDR_ERR R/W1C 0b SPI register address error.
This bit indicates an invalid register read or write address. The valid address range is 00h to 50h for both devices. Except for the STATUS register, register write operations are blocked when the error is set. Clear the error by writing 1b. Address error check is enabled by setting SPI_ADDR_EN = 1b.
0b = No error
1b = Invalid register read/write address
0 SCLK_ERR R/W1C 0b SPI SCLK count error.
This bit indicates the number of SCLK cycles was not a multiple of eight. Except for the STATUS register, register write operations are blocked when the flag is set. Clear the error by writing 1b. SCLK count error check is enabled by setting SCLK_CNT_EN = 1b.
0b = No error
1b = Number of SCLK clock cycles is not a multiple of eight

8.4 CLK_CNT Register (Address = 03h) [Reset = 00h]

CLK_CNT is described in Table 8-6.

Table 8-6 CLK_CNT Register Description
Bit Field Type Reset Description
7-0 CLK_CNT[7:0] R 00000000b Clock count value register.
This register is a counter of the ADC clock. The counter increments at a rate of fCLK / 32, divided by the CLK_DIV[2:0] setting. Read the register at known intervals to verify the ADC clock frequency. The clock count is enabled by the CLK_CNT_EN register bit. When enabled, the counter value resets to 00h. When disabled, the count value is 00h.

8.5 GPIO_RD Register (Address = 04h) [Reset = 00h]

GPIO_RD is shown in Figure 8-2 and described in Table 8-7.

Figure 8-2 GPIO_RD Register
7 6 5 4 3 2 1 0
GPIO_RD7 GPIO_RD6 GPIO_RD5 GPIO_RD4 GPIO_RD3 GPIO_RD2 GPIO_RD1 GPIO_RD0
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 8-7 GPIO_RD Register Field Descriptions
Bit Field Type Reset Description
7-0 GPIO_RD[7:0] R 00000000b GPIO read data register.
These bits are the read values of GPIO. If the GPIO is programmed as an output, the value returned is from the GPIO pin.

8.6 CRC_MSB, CRC_LSB Registers (Addresses = 05h, 06h) [Reset = 00h]

CRC registers described in Table 8-8.

Table 8-8 CRC Registers Description
Name Address Type Reset Description
CRC_MSB
CRC_LSB		 5h
6h		 R/W
R/W		 00h
00h		 Two-byte register map CRC value.
Write a 16-bit CRC value, computed over the register range 08h to 50h. The register map CRC check is enabled by the REG_CRC_EN bit. The CRC error is reported to the REG_ERR bit of the STATUS register.

8.7 CONTROL Register (Address = 07h) [Reset = 00h]

CONTROL is shown in Figure 8-3 and described in Table 8-9.

Figure 8-3 CONTROL Register
7 6 5 4 3 2 1 0
RESET[5:0] START STOP
R/W-000000b R/W-0b R/W-0b
Table 8-9 CONTROL Register Field Descriptions
Bit Field Type Reset Description
7-2 RESET[5:0] R/W 000000b Software reset.
Write the value of 010110b to reset the ADC. Make sure the START or STOP bits are also 0b in the same write operation. These bits self-clear and always read 000000b.
1 START R/W 0b START conversions.
Start channel conversions by writing 1b. This bit also restarts an ongoing conversion. Conversions continue until 1b is written to the STOP bit. This bit self-clears after written, therefore always reads 0b. This bit is not functional in synchronized control mode.
0b = No operation
1b = Start or restart conversions
0 STOP R/W 0b Stop conversions.
Stop channel conversions by writing 1b. This bit self-clears after written, therefore always reads 0b. This bit is not functional in synchronized control mode.
0b = No operation
1b = Stop conversions on all channels

8.8 GEN_CFG1 Register (Address = 08h) [Reset = 00h]

GEN_CFG1 is shown in Figure 8-4 and described in Table 8-10.

Figure 8-4 GEN_CFG1 Register
7 6 5 4 3 2 1
RESERVED DELAY[2:0] VCM REFP_BUF REF_RNG
R-00b R/W-000b R/W-0b R/W-0b R/W-0b
Table 8-10 GEN_CFG1 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 00b Reserved.
5-3 DELAY[2:0] R/W 000b Conversion start delay time selection.
Select the conversion start delay time in number of fMOD cycles after taking START high (or setting the START bit).
000b = 0
001b = 4
010b = 8
011b = 16
100b = 32
101b = 128
110b = 512
111b = 1024
2 VCM R/W 0b Common-mode voltage output enable.
This bit enables the common-mode voltage output of the VCM pin. The VCM output voltage is equal to (AVDD1 + AVSS) / 2.
0b = Disabled
1b = Enabled
1 REFP_BUF R/W 0b Reference positive buffer enable.
This bit enables the REFP pin precharge buffer.
0b = Disabled
1b = Enabled
0 REF_RNG R/W 0b Voltage reference range selection.
This bit selects the low or high voltage operating range of the reference input. Program the range to match the actual reference voltage.
0b = Low-voltage reference range
1b = High-voltage reference range

8.9 GEN_CFG2 Register (Address = 09h) [Reset = 04h]

GEN_CFG2 is shown in Figure 8-5 and described in Table 8-11.

Figure 8-5 GEN_CFG2 Register
7 6 5 4 3 2 1 0
AVG_MODE[1:0] RESERVED START_MODE[1:0] SPEED_MODE[1:0] STBY_MODE
R/W-00b R-0b R/W-00b R/W-10b R/W-0b
Table 8-11 GEN_CFG2 Register Field Descriptions
Bit Field Type Reset Description
7-6 AVG_MODE[1:0] R/W 00b Channel averaging mode.
Select the number of channels to average. See the Data Averaging section for more details.
00b = Disabled
01b = Average in groups of two
10b = Average in groups of four
11b = Average in a group of eight (ADS127L18)
5 RESERVED R 0b Reserved
4-3 START_MODE[1:0] R/W 00b START mode selection.
These bits program the functional mode of the START pin. See the Synchronization section for more details.
00b = Start/stop control mode
01b = Reserved
10b = Synchronized control mode
11b = Reserved
2-1 SPEED_MODE[1:0] R/W 10b Speed mode selection.
These bits program the device speed mode.
00b = Low-speed mode (fCLK = 3.2MHz)
01b = Mid-speed mode (fCLK = 12.8MHz)
10b = High-speed mode (fCLK = 25.6MHz)
11b = Max-speed mode (fCLK = 32.768MHz)
0 STBY_MODE R/W 0b Standby mode selection.
This bit enables the standby mode when conversions are stopped. Standby mode reduces power consumption compared to the idle mode.
0b = Idle mode, device fully powered
1b = Standby mode, analog section of channels powered down

8.10 GEN_CFG3 Register (Address = 0Ah) [Reset = 80h]

GEN_CFG3 is shown in Figure 8-6 and described in Table 8-12.

Figure 8-6 GEN_CFG3 Register
7 6 5 4 3 2 1 0
OUT_DRV DATA CLK_CNT_EN SPI_STAT_EN SPI_ADDR_EN SCLK_CNT_EN SPI_CRC_EN REG_CRC_EN
R/W-1b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-12 GEN_CFG3 Register Field Descriptions
Bit Field Type Reset Description
7 OUT_DRV R/W 1b Digital output drive selection.
Select the digital output driver strength. Full drive strength increases the slew rate of the output signal.
0b = Full-power driver strength
1b = Half-power driver strength
6 DATA R/W 0b Data resolution selection.
This bit selects the output data resolution.
0b = 24-bit resolution
1b = 16-bit resolution
5 CLK_CNT_EN R/W 0b Clock counter enable.
This bit enables the ADC clock counter register.
0b = Disabled
1b = Enabled
4 SPI_STAT_EN R/W 0b SPI status byte output enable.
This bit enables the STATUS register value in the SPI output.
0b = Disabled
1b = Enabled
3 SPI_ADDR_EN R/W 0b SPI register address enable.
This bit enables the SPI address verification. The ADDR_ERR bit of the STATUS register sets if the register read or write address is invalid.
0b = Disabled
1b = Enabled
2 SCLK_CNT_EN R/W 0b SCLK count enable.
This bit enables the SPI SCLK count verification. The SCLK_ERR bit of the STATUS register sets if the number of SCLK cycles in a frame are not multiples of 8.
0b = Disabled
1b = Enabled
1 SPI_CRC_EN R/W 0b SPI CRC enable.
This bit enables the SPI CRC output byte and the input data CRC check. The SPI_ERR bit of the STATUS byte sets if the input CRC is in error. Write 1b to the SPI_ERR bit to clear the error.
0b = Disabled
1b = Enabled
0 REG_CRC_EN R/W 0b Register map CRC enable.
This bit enables the register map CRC error verification. The REG_ERR bit of the STATUS byte sets if the CRC value is not correct.
0b = Disabled
1b = Enabled

DP_CFG1 Register (Address = 0Bh) [Reset = 20h]

DP_CFG1 is shown in Figure 8-7 and described in Table 8-13.

Figure 8-7 DP_CFG1 Register
7 6 5 4 3 2 1 0
DP_CRC_EN DP_STAT_EN DP_TDM[1:0] RESERVED DP_DAISY RESERVED
R/W-0b R/W-0b R/W-10b R-00b R/W-0b R-0b
Table 8-13 DP_CFG1 Register Field Descriptions
Bit Field Type Reset Description
7 DP_CRC_EN R/W 0b Data port CRC byte enable.
This bit enables the data port CRC byte. A CRC byte is appended to the end of the channel data.
0b = Disabled
1b = Enabled
6 DP_STAT_EN R/W 0b Data port status byte enable.
This bit enables the data port status byte. The status byte is prefixed to the beginning of the channel data.
0b = Disabled
1b = Enabled
5-4 DP_TDM[1:0] R/W 10b Data port time division multiplexing (TDM) configuration.
These bits select the number of data lanes. See the Time Division Multiplexing section for details.
00b = One data lane
01b = One (ADS127L14) / two data lanes (ADS127L18)
10b = Two (ADS127L14) / four data lanes (ADS127L18)
11b = Four (ADS127L14) / eight data lanes (ADS127L18)
3-2 RESERVED R 00b Reserved.
1 DP_DAISY R/W 0b Data port daisy-chain mode.
This bit selects daisy-chain or repeat data modes.
0b = TDM data mode. DINx data are shifted-in and appended to the original channel data.
1b = Repeat data mode. Original channel data are repeated and DINx data are ignored.
0 RESERVED R 0b Reserved.

8.11 DP_CFG2 Register (Address = 0Ch) [Reset = 00h]

DP_CFG2 is shown in Figure 8-8 and described in Table 8-14.

Figure 8-8 DP_CFG2 Register
7 6 5 4 3 2 1 0
RESERVED DCLK_DIV[1:0] DOUT_DLY[4:0]
R-0b R/W-00b R/W-00000b
Table 8-14 DP_CFG2 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0b Reserved
6-5 DCLK_DIV[1:0] R/W 00b Data port DCLK frequency divider.
These bits select the frame-sync DCLK frequency.
00b = Divide by 1
01b = Divide by 2
10b = Divide by 4
11b = Divide by 8
4-0 DOUT_DLY[4:0] R/W 00000b Data port DOUTx delay.
These bits select the delay or advance of the DOUTx signals relative to the DCLK and FSYNC signals. Positive values advance the DOUTx signals; negative values delay the DOUTx signals. The bit weight is approximately 0.3ns. See the Data Port Offset Timing section for details.

8.12 CLK_CFG Register (Address = 0Dh) [Reset = 00h]

CLK_CFG is shown in Figure 8-9 and described in Table 8-15.

Figure 8-9 CLK_CFG Register
7 6 5 4 3 2 1 0
RESERVED CLK_SEL CLK_DIV[2:0]
R-0000b R/W-0b R/W-000b
Table 8-15 CLK_CFG Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0000b Reserved.
3 CLK_SEL R/W 0b ADC clock selection.
This bit selects the internal oscillator or external clock operation.
0b = Internal oscillator
1b = External clock
2-0 CLK_DIV[2:0] R/W 000b ADC clock divider.
These bits select the clock signal divider for both external clock and internal oscillator.
000b = Divide by 1
001b = Divide by 2
010b = Divide by 3
011b = Divide by 4
100b - 111b = Divide by 8

8.13 GPIO_WR Register (Address = 0Eh) [Reset = 00h]

GPIO_WR is shown in Figure 8-10 and described in Table 8-16.

Figure 8-10 GPIO_WR Register
7 6 5 4 3 2 1 0
GPIO_WR7 GPIO_WR6 GPIO_WR5 GPIO_WR4 GPIO_WR3 GPIO_WR2 GPIO_WR1 GPIO_WR0
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-16 GPIO_WR Register Field Descriptions
Bit Field Type Reset Description
7-0 GPIO_WR[7:0] R/W 00000000b GPIO write data.
This register is the GPIO write data register. Set the direction of the GPIO pins to output mode to write the value. See the GPIO_RD register to read GPIO data.
0b = GPIO pin is driven low
1b = GPIO pin is driven high

8.14 GPIO_DIR Register (Address = 0Fh) [Reset = 00h]

GPIO_DIR is shown in Figure 8-11 and described in Table 8-17.

Figure 8-11 GPIO_DIR Register
7 6 5 4 3 2 1 0
GPIO_DIR7 GPIO_DIR6 GPIO_DRI5 GPIO_DIR4 GPIO_DIR3 GPIO_DIR2 GPIO_DIR1 GPIO_DIR0
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-17 GPIO_DIR Register Field Descriptions
Bit Field Type Reset Description
7-0 GPIO_DIR[7:0] R/W 00000000b GPIO direction.
This register programs the GPIO direction as inputs or outputs.
0b = The GPIO pin is an output
1b = The GPIO pin is an input

8.15 GPIO_EN Register (Address = 10h) [Reset = 00h]

GPIO_EN is shown in Figure 8-12 and described in Table 8-18.

Figure 8-12 GPIO_EN Register
7 6 5 4 3 2 1 0
GPIO_EN7 GPIO_EN6 GPIO_EN5 GPIO_EN4 GPIO_EN3 GPIO_EN2 GPIO_EN1 GPIO_EN0
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-18 GPIO_EN Register Field Descriptions
Bit Field Type Reset Description
7-0 GPIO_EN[7:0] R/W 00000000b GPIO enable.
This register enables the GPIO function for each pin. When enabled, the GPIO pin function has priority over other pin functions.
0b = GPIO pin is disabled
1b = GPIO pin is enabled

8.16 CHn_CFG1 Registers (Address = Channel Number × 08h + 11h) [Reset = 00h]

Channel n configuration 1 register addresses are shown in Table 8-19. The register bit map is shown in Figure 8-13 and described in Table 8-20.

Table 8-19 CHn_CFG1 Register Addresses
NAME DESCRIPTION ADDRESS
CH0_CFG1 Channel 0 configuration 1 11h
CH1_CFG1 Channel 1 configuration 1 19h
CH2_CFG1 Channel 2 configuration 1 21h
CH3_CFG1 Channel 3 configuration 1 29h
CH4_CFG1 Channel 4 configuration 1 31h
CH5_CFG1 Channel 5 configuration 1 39h
CH6_CFG1 Channel 6 configuration 1 41h
CH7_CFG1 Channel 7 configuration 1 49h
Figure 8-13 CHn_CFG1 Register
7 6 5 4 3 2 1 0
RESERVED CHn_MUX[2:0] CHn_INP_RNG CHn_EX_RNG CHn_BUFN CHn_BUFP
R-0b R/W-000b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-20 CHn_CFG1 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0b Reserved
6-4 CHn_MUX[2:0] R/W 000b Channel input multiplexer selection.
These bits select between the signal input or input test modes. See the Analog Inputs (AINP, AINN) section for details.
000b = Normal input polarity
001b = Reverse input polarity
010b = Offset and noise test: Internal short to mid supply
011b = CMRR test to AINP
100b = CMRR test to AINN
101b = –FS test
110b = +FS test
111b = +FS test
3 CHn_INP_RNG R/W 0b Channel input range selection.
This bit selects the 1x or 2x input range. See the Input Range section for more details.
0b = 1x input range
1b = 2x input range
2 CHn_EX_RNG R/W 0b Channel extended input range selection.
This bit extends the input range by 25%. See the Input Range section for more details.
0b = Disabled
1b = Enabled: The FS range is extended by 25%
1 CHn_BUFN R/W 0b Channel analog input negative buffer enable.
This bit enables the channel AINN precharge buffer.
0b = Disabled
1b = Enabled
0 CHn_BUFP R/W 0b Channel analog input positive buffer enable.
This bit enables the channel AINP precharge buffer.
0b = Disabled
1b = Enabled

8.17 CHn_CFG2 Registers (Address = Channel Number × 08h + 12h) [Reset = 00h]

Channel n configuration 2 register addresses are shown in Table 8-21. The register bit map is shown in Figure 8-14 and described in Table 8-22.

Table 8-21 CHn_CFG2 Register Addresses
NAME REGISTER DESCRIPTION ADDRESS
CH0_CFG2 Channel 0 configuration 2 12h
CH1_CFG2 Channel 1 configuration 2 1Ah
CH2_CFG2 Channel 2 configuration 2 22h
CH3_CFG2 Channel 3 configuration 2 2Ah
CH4_CFG2 Channel 4 configuration 2 32h
CH5_CFG2 Channel 5 configuration 2 3Ah
CH6_CFG2 Channel 6 configuration 2 42h
CH7_CFG2 Channel 7 configuration 2 4Ah
Figure 8-14 CHn_CFG2 Register
7 6 5 4 3 2 1 0
RESERVED CHn_PWDN CHn_FLTR[4:0]
R-00b R/W-0b R/W-00000b
Table 8-22 CHn_CFG2 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 00b Reserved.
5 CHn_PWDN R/W 0b Channel power-down mode selection.
When set, the ADC channel is powered down. When powered down, channel data are the last remaining data.
0b = Active
1b = Powered down
4-0 CHn_FLTR[4:0] R/W 00000b Channel digital filter and data rate selection.
These bits configure the digital filter and data rate for each channel. The data rate between channels must be related by power of 2. The device has five filter configurations: wideband, sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1. See the Digital Filter section for the data rate corresponding to the OSR.
00000b = Wideband: OSR = 32
00001b = Wideband: OSR = 64
00010b = Wideband: OSR = 128
00011b = Wideband: OSR = 256
00100b = Wideband: OSR = 512
00101b = Wideband: OSR = 1024
00110b = Wideband: OSR = 2048
00111b = Wideband: OSR = 4096
01000b = Sinc4: OSR = 12
01001b = Sinc4: OSR = 16
01010b = Sinc4: OSR = 24
01011b = Sinc4: OSR = 32
01100b = Sinc4: OSR = 64
01101b = Sinc4: OSR = 128
01110b = Sinc4: OSR = 256
01111b = Sinc4: OSR = 512
10000b = Sinc4: OSR = 1024
10001b = Sinc4: OSR = 2048
10010b = Sinc4: OSR = 4096
10011b = Sinc4: OSR = 32 + sinc1: OSR = 2
10100b = Sinc4: OSR = 32 + sinc1: OSR = 4
10101b = Sinc4: OSR = 32 + sinc1: OSR = 10
10110b = Sinc4: OSR = 32 + sinc1: OSR = 20
10111b = Sinc4: OSR = 32 + sinc1: OSR = 40
11000b = Sinc4: OSR = 32 + sinc1: OSR = 100
11001b = Sinc4: OSR = 32 + sinc1: OSR = 200
11010b = Sinc4: OSR = 32 + sinc1: OSR = 400
11011b = Sinc4: OSR = 32 + sinc1: OSR = 1000
11100b = Sinc3: OSR = 26667
11101b = Sinc3: OSR = 32000
11110b = Sinc3: OSR = 32000 + sinc1: OSR = 3
11111b = Sinc3: OSR = 32000 + sinc1: OSR = 5

8.18 CHn Offset Registers [Reset = 000000h]

Channel n offset registers are described in Table 8-23.

Table 8-23 CHn Offset Registers Description
NAME ADDRESS TYPE RESET DESCRIPTION
MSB MID LSB
Channel 0 offset 13h 14h 15h R/W 000000h These registers are three-byte offset registers.
Three registers form the 24-bit offset calibration word of each channel. The offset value is in two's-complement representation and is subtracted from the conversion result. The offset operation precedes the gain operation. In 16-bit mode, conversion data are left-justified to the 24-bit offset value.
Channel 1 offset 1Bh 1Ch 1Dh
Channel 2 offset 23h 24h 25h
Channel 3 offset 2Bh 2Ch 2Dh
Channel 4 offset 33h 34h 35h
Channel 5 offset 3Bh 3Ch 3Dh
Channel 6 offset 43h 44h 45h
Channel 7 offset 4Bh 4Ch 4Dh

8.19 CHn Gain Registers [Reset = 400000h]

Channel n gain registers are described in Table 8-24.

Table 8-24 CHn Gain Registers Description
NAME ADDRESS TYPE RESET DESCRIPTION
MSB MID LSB
Channel 0 gain 16h 17h 18h R/W 400000h These registers are three-byte gain registers.
Three registers form the 24-bit gain calibration word of each channel. The gain value is in straight-binary representation and is normalized to 400000h for gain = 1. The conversion data are multiplied by GAIN[23:0] / 400000h after the offset operation.
Channel 1 gain 1Eh 1Fh 20h
Channel 2 gain 26h 27h 28h
Channel 3 gain 2Eh 2Fh 30h
Channel 4 gain 36h 37h 38h
Channel 5 gain 3Eh 3Fh 40h
Channel 6 gain 46h 47h 48h
Channel 7 gain 4Eh 4Fh 50h