SBASAM0B March 2024 – November 2024 ADS127L18
PRODMIX
The ADC provides external clock operation. To select external clock operation in SPI programming mode, set the CLK_SEL bit to 1 and apply the clock signal to the CLKIN pin. In the hardware programming mode, only external clock operation is possible.
If desired, decrease the clock frequency from nominal specified frequency to yield specific data rates between the available OSR values. When doing so, the conversion noise at the reduced data rate is the same as the original frequency. Reduction of conversion noise is only possible by increasing the digital filter OSR value or changing the speed or filter modes.
Clock jitter results in timing variations of the modulator sampling that leads to degraded SNR performance. A low-jitter clock is essential to meet data sheet SNR performance. For example, with a 200kHz signal frequency, an external clock with < 10ps (rms) jitter is required. For lower signal frequencies, the clock jitter is relaxed by –20dB per decade of signal frequency reduction. For example, with fIN = 20kHz, a clock with 100ps jitter is acceptable. Many types of RC oscillators exhibit high levels of jitter that are to be avoided for ac signal measurement. Instead, use a crystal oscillator or an integrated circuit clock source. Avoid ringing at the clock input. A series resistor placed at the output of the clock buffer helps reduce ringing.