SBASAM0B March   2024  – November 2024 ADS127L18

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Clock Dividers
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 External Clock
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
        2. 7.3.8.2 Low-Latency Filter (Sinc)
          1. 7.3.8.2.1 Sinc4 Filter
          2. 7.3.8.2.2 Sinc4 + Sinc1 Cascade Filter
          3. 7.3.8.2.3 Sinc3 Filter
          4. 7.3.8.2.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Reset
        1. 7.4.1.1 RESET Pin
        2. 7.4.1.2 Reset by SPI Register
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2  Idle and Standby Modes
      3. 7.4.3  Power-Down
      4. 7.4.4  Speed Modes
      5. 7.4.5  Synchronization
        1. 7.4.5.1 Synchronized Control Mode
        2. 7.4.5.2 Start/Stop Control Mode
      6. 7.4.6  Conversion-Start Delay Time
      7. 7.4.7  Calibration
        1. 7.4.7.1 Offset Calibration Registers
        2. 7.4.7.2 Gain Calibration Registers
        3. 7.4.7.3 Calibration Procedure
      8. 7.4.8  Data Averaging
      9. 7.4.9  Diagnostics
        1. 7.4.9.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.9.2 SPI CRC
        3. 7.4.9.3 Register Map CRC
        4. 7.4.9.4 ADC Error
        5. 7.4.9.5 SPI Address Range
        6. 7.4.9.6 SCLK Counter
        7. 7.4.9.7 Clock Counter
        8. 7.4.9.8 Frame-Sync CRC
        9. 7.4.9.9 Self Test
      10. 7.4.10 Frame-Sync Data Port
        1. 7.4.10.1  Data Packet
        2. 7.4.10.2  Data Format
        3. 7.4.10.3  STATUS_DP Header Byte
        4. 7.4.10.4  FSYNC Pin
        5. 7.4.10.5  DCLK Pin
        6. 7.4.10.6  DOUTx Pins
        7. 7.4.10.7  DINx Pins
        8. 7.4.10.8  Time Division Multiplexing
        9. 7.4.10.9  Daisy Chain
        10. 7.4.10.10 DOUTx Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 Commands
        1. 7.5.4.1 Write Register Command
        2. 7.5.4.2 Read Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 AVDD1 and AVSS
      2. 9.3.2 AVDD2
      3. 9.3.3 IOVDD
      4. 9.3.4 CAPA and CAPD
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
7.3.8.2.2 Sinc4 + Sinc1 Cascade Filter

The sinc4 + sinc1 filter is the cascade of the sinc4 filter and a sinc1 filters. The fixed OSR of the sinc4 stage (OSR = 32) multiplied by the OSR of the sinc1 stage determines the ADC output data rate. The sinc4 + sinc1 filter mode has shorter latency time than the single-stage sinc4 filter. Table 7-5 summarizes the sinc4 + sinc1 filter characteristics.

Table 7-5 Sinc4 + Sinc1 Cascade Filter Characteristics
MODE fCLK
(MHz)		 OSR
(A × B)(2)		 DATA RATE
(kSPS)		 –3dB FREQUENCY
(kHz)		 LATENCY TIME
(µs)(1)
Max speed 32.768 64
(32 × 2)		 256 87.49 10.9
High speed 25.6 200 68.35 13.9
Mid speed 12.8 100 34.18 27.9
Low speed 3.2 25 8.544 111
Max speed 32.768 128
(32 × 4)		 128 52.44 14.8
High speed 25.6 100 40.97 19.0
Mid speed 12.8 50 20.49 37.9
Low speed 3.2 12.5 5.121 152
Max speed 32.768 320
(32 × 10)		 51.2 22.36 26.5
High speed 25.6 40 17.47 34.0
Mid speed 12.8 20 8.735 67.9
Low speed 3.2 5 2.184 272
Max speed 32.768 640
(32 × 20)		 25.6 11.28 46.0
High speed 25.6 20 8.814 58.9
Mid speed 12.8 10 4.407 118
Low speed 3.2 2.5 1.102 471
Max speed 32.768 1280
(32 × 40)		 12.8 5.658 85.1
High speed 25.6 10 4.420 109
Mid speed 12.8 5 2.210 218
Low speed 3.2 1.25 0.552 871
Max speed 32.768 3200
(32 × 100)		 5.12 2.266 202
High speed 25.6 4 1.770 259
Mid speed 12.8 2 0.885 517
Low speed 3.2 0.5 0.221 2068
Max speed 32.768 6400
(32 × 200)		 2.56 1.133 398
High speed 25.6 2 0.885 509
Mid speed 12.8 1 0.443 1018
Low speed 3.2 0.25 0.111 4075
Max speed 32.768 12800
(32 × 400)		 1.28 0.566 788
High speed 25.6 1 0.442 1008
Mid speed 12.8 0.5 0.221 2017
Low speed 3.2 0.125 0.055 8069
Max speed 32.768 32000
(32 × 1000)		 0.512 0.226 1960
High speed 25.6 0.4 0.177 2508
Mid speed 12.8 0.2 0.089 5018
Low speed 3.2 0.05 0.022 20070
(1) Latency time increases by 8 / fCLK (µs) when the analog input buffers are enabled.
(2) A = First stage OSR, B = Second stage OSR.

Figure 7-20 illustrates the frequency response of the sinc4 + sinc1 filter for three OSR values. The combined frequency response is the overlaid response of the sinc4 and sinc1 filters. For low OSR values, the response profile is dominated by the roll-off of the sinc4 filter. Nulls in the frequency response occur at n · fDATA, n = 1, 2, 3, and so on. At the null frequencies, the filter has zero gain.

ADS127L14 ADS127L18 Sinc4 + Sinc1 Frequency Response Figure 7-20 Sinc4 + Sinc1 Frequency Response