SBASAU2 May   2024 PCM1841-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Timing Diagram
    9. 5.9 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Hardware Control
      2. 6.3.2 Audio Serial Interfaces
        1. 6.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 6.3.2.2 Inter IC Sound (I2S) Interface
        3. 6.3.2.3 Left-Justified (LJ) Interface
      3. 6.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4 Input Channel Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Microphone Bias
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 Digital High-Pass Filter
        2. 6.3.7.2 Configurable Digital Decimation Filters
          1. 6.3.7.2.1 Linear Phase Filters
            1. 6.3.7.2.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 6.3.7.2.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 6.3.7.2.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 6.3.7.2.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 6.3.7.2.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 6.3.7.2.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 6.3.7.2.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 6.3.7.2.2 Low-Latency Filters
            1. 6.3.7.2.2.1 Sampling Rate: 16kHz or 14.7kHz
            2. 6.3.7.2.2.2 Sampling Rate: 24kHz or 22.05kHz
            3. 6.3.7.2.2.3 Sampling Rate: 32kHz or 29.4kHz
            4. 6.3.7.2.2.4 Sampling Rate: 48kHz or 44.1kHz
            5. 6.3.7.2.2.5 Sampling Rate: 96kHz or 88.2kHz
      8. 6.3.8 Dynamic Range Enhancer (DRE)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Shutdown
      2. 6.4.2 Active Mode
  8. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9Revision History
  11.   Mechanical, Packaging, and Orderable Information

Left-Justified (LJ) Interface

The standard LJ protocol is defined for only two channels: left and right. In LJ mode, the MSB of the left slot 0 is transmitted in the same BCLK cycle after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. The MSB of the right slot 0 is transmitted in the same BCLK cycle after the falling edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. In controller mode, FSYNC is transmitted on the rising edge of BCLK. Figure 6-7 and Figure 6-8 illustrate the protocol timing for LJ operation in target and controller mode of operation.

PCM1841-Q1 LJ Mode Protocol Timing
                                                  In Target ModeFigure 6-7 LJ Mode Protocol Timing In Target Mode
PCM1841-Q1 LJ Mode Protocol Timing
                                                  In Controller ModeFigure 6-8 LJ Mode Protocol Timing In Controller Mode

For proper operation of the audio bus in LJ mode, the number of bit clocks per frame must be greater than, or equal to, the number of active output channels (including left and right slots) times the 32-bit word length of the output channel data. The device FSYNC high pulse must be atleast Word length(32-bits) times number of active left channels, BCLK cycles wide. Similarly, the FSYNC low pulse must be atleast Word length(32-bits) times number of active right channels, BCLK cycles wide. The device transmits zero data value on SDOUT for the extra unused bit clock cycles.