SBASAU2 May   2024 PCM1841-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Timing Diagram
    9. 5.9 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Hardware Control
      2. 6.3.2 Audio Serial Interfaces
        1. 6.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 6.3.2.2 Inter IC Sound (I2S) Interface
        3. 6.3.2.3 Left-Justified (LJ) Interface
      3. 6.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4 Input Channel Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Microphone Bias
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 Digital High-Pass Filter
        2. 6.3.7.2 Configurable Digital Decimation Filters
          1. 6.3.7.2.1 Linear Phase Filters
            1. 6.3.7.2.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 6.3.7.2.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 6.3.7.2.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 6.3.7.2.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 6.3.7.2.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 6.3.7.2.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 6.3.7.2.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 6.3.7.2.2 Low-Latency Filters
            1. 6.3.7.2.2.1 Sampling Rate: 16kHz or 14.7kHz
            2. 6.3.7.2.2.2 Sampling Rate: 24kHz or 22.05kHz
            3. 6.3.7.2.2.3 Sampling Rate: 32kHz or 29.4kHz
            4. 6.3.7.2.2.4 Sampling Rate: 48kHz or 44.1kHz
            5. 6.3.7.2.2.5 Sampling Rate: 96kHz or 88.2kHz
      8. 6.3.8 Dynamic Range Enhancer (DRE)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Shutdown
      2. 6.4.2 Active Mode
  8. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9Revision History
  11.   Mechanical, Packaging, and Orderable Information

5.7 Switching Characteristics: TDM, I2S or LJ Interface

at TA = 25°C, IOVDD = 3.3V or 1.8V and 20pF load on all outputs (unless otherwise noted); see Figure 5-1 for timing diagram
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(SDOUT-BCLK) BCLK to SDOUT delay 50% of BCLK to 50% of SDOUT 18 ns
td(SDOUT-FSYNC) FSYNC to SDOUT delay in TDM or LJ mode (for MSB data with TX_OFFSET = 0) 50% of FSYNC to 50% of SDOUT 18 ns
f(BCLK) BCLK output clock frequency: controller mode (1) 24.576 MHz
tH(BCLK) BCLK high pulse duration: controller mode 14 ns
tL(BCLK) BCLK low pulse duration: controller mode 14 ns
td(FSYNC) BCLK to FSYNC delay: controller mode 50% of BCLK to 50% of FSYNC 18 ns
tr(BCLK) BCLK rise time: controller mode 10% - 90% rise time 8 ns
tf(BCLK) BCLK fall time: controller mode 90% - 10% fall time 8 ns
(1) The BCLK output clock frequency must be lower than 18.5MHz (to meet the timing specifications), if the SDOUT data line is latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.