SBASAV2
October 2024
ADS9212
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements
5.7
Switching Characteristics
5.8
Timing Diagrams
5.9
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Analog Inputs
6.3.1.1
Input Clamp Protection Circuit
6.3.1.2
Programmable Gain Amplifier (PGA)
6.3.1.3
Wide-Common-Mode Voltage Rejection Circuit
6.3.1.4
Gain Error Calibration
6.3.2
ADC Transfer Function
6.3.3
ADC Sampling Clock Input
6.3.4
Reference
6.3.4.1
Internal Reference Voltage
6.3.4.2
External Reference Voltage
6.3.5
Data Interface
6.3.5.1
Data Clock Output
6.3.5.2
ADC Output Data Randomizer
6.3.5.3
Test Patterns for Data Interface
6.3.5.3.1
Fixed Pattern
6.3.5.3.2
Digital Ramp
6.3.5.3.3
Alternating Test Pattern
6.4
Device Functional Modes
6.4.1
Power-Down
6.4.2
Reset
6.4.3
Initialization Sequence
6.4.4
Normal Operation
6.5
Programming
6.5.1
Register Write
6.5.2
Register Read
6.5.3
Multiple Devices: Daisy-Chain Topology for SPI Configuration
6.5.3.1
Register Write With Daisy-Chain
6.5.3.2
Register Read With Daisy-Chain
7
Register Map
7.1
Register Bank 0
7.2
Register Bank 1
7.3
Register Bank 2
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Parametric Measurement Unit (PMU)
8.2.2
Design Requirements
8.2.3
Detailed Design Procedure
8.2.4
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
Support Resources
9.3
Trademarks
9.4
Electrostatic Discharge Caution
9.5
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
5.8
Timing Diagrams
Figure 5-1
SPI Configuration Interface
Figure 5-2
4-SDO DDR CMOS Data Interface
Figure 5-3
2-SDO DDR CMOS Data Interface
Figure 5-4
4-SDO SDR CMOS Data Interface
Figure 5-5
2-SDO SDR CMOS Data Interface