SBASAZ5 October 2024 AMC0386-Q1
ADVANCE INFORMATION
If a fullscale input signal is applied to the AMC0386-Q1, the device generates a single one or zero every 128 bits at DOUT. Figure 6-4 shows a timing diagram of this process. A single 1 or 0 is generated depending on the actual polarity of the signal being sensed. A fullscale signal is defined as |VSNSP – VSNSN| ≥ |VClipping|. In this way, differentiating between a missing AVDD and a fullscale input signal is possible on the system level.