SBASB12 May   2024 PCM1809

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Hardware Control
      2. 6.3.2 Audio Serial Interfaces
        1. 6.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 6.3.2.2 Inter IC Sound (I2S) Interface
      3. 6.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4 Input Channel Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Signal-Chain Processing
        1. 6.3.6.1 Digital High-Pass Filter
        2. 6.3.6.2 Configurable Digital Decimation Filters
          1. 6.3.6.2.1 Linear Phase Filters
            1. 6.3.6.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 6.3.6.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 6.3.6.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 6.3.6.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 6.3.6.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 6.3.6.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 6.3.6.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
          2. 6.3.6.2.2 Low-Latency Filters
            1. 6.3.6.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 6.3.6.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 6.3.6.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 6.3.6.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 6.3.6.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.3.3 Phase-Locked Loop (PLL) and Clock Generation

The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the ADC modulator and digital filter engine, as well as other control blocks.

In target mode of operation, the device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming. Table 6-3 and Table 6-4 list the supported FSYNC and BCLK frequencies.

Table 6-3 Supported FSYNC (Multiples or Submultiples of 48kHz) and BCLK Frequencies
BCLK TO FSYNC RATIOBCLK (MHz)
FSYNC
(8kHz)		FSYNC
(16kHz)		FSYNC
(24kHz)		FSYNC
(32kHz)		FSYNC
(48kHz)		FSYNC
(96kHz)		FSYNC
(192kHz)
16Reserved0.2560.3840.5120.7681.5363.072
24Reserved0.3840.5760.7681.1522.3044.608
320.2560.5120.7681.0241.5363.0726.144
480.3840.7681.1521.5362.3044.6089.216
640.5121.0241.5362.0483.0726.14412.288
960.7681.5362.3043.0724.6089.21618.432
1281.0242.0483.0724.0966.14412.28824.576
1921.5363.0724.6086.1449.21618.432Reserved
2562.0484.0966.1448.19212.28824.576Reserved
3843.0726.1449.21612.28818.432ReservedReserved
5124.0968.19212.28816.38424.576ReservedReserved
Table 6-4 Supported FSYNC (Multiples or Submultiples of 44.1kHz) and BCLK Frequencies
BCLK TO FSYNC RATIOBCLK (MHz)
FSYNC
(7.35kHz)		FSYNC
(14.7kHz)		FSYNC
(22.05kHz)		FSYNC
(29.4kHz)		FSYNC
(44.1kHz)		FSYNC
(88.2kHz)		FSYNC
(176.4kHz)
16ReservedReserved0.35280.47040.70561.41122.8224
24Reserved0.35280.52920.70561.05842.11684.2336
32Reserved0.47040.70560.94081.41122.82245.6448
480.35280.70561.05841.41122.11684.23368.4672
640.47040.94081.41121.88162.82245.644811.2896
960.70561.41122.11682.82244.23368.467216.9344
1280.94081.88162.82243.76325.644811.289622.5792
1921.41122.82244.23365.64488.467216.9344Reserved
2561.88163.76325.64487.526411.289622.5792Reserved
3842.82245.64488.467211.289616.9344ReservedReserved
5123.76327.526411.289615.052822.5792ReservedReserved

In the controller mode of operation, the device uses the MD1 pin (as the system clock, MCLK) as the reference input clock source with a supported system clock frequency option of either 256 × fS or 512 × fS as configured using the MD0 pin. controller mode supports fS rates of 44.1kHz and 48kHz. Table 6-5 shows the system clock selection for the controller mode using the MD0 pin.

Table 6-5 System Clock Selection for the Controller Mode
MD0SYSTEM CLOCK SELECTION (Valid for Controller Mode Only)
LOWSystem clock with frequency 256 × fS connected to the MD1 pin as MCLK
HIGHSystem clock with frequency 512 × fS connected to the MD1 pin as MCLK

See Table 6-7 and for the MD0 and MD1 pin function in the target mode of operation.