The ADS8568 has several static digital configuration pins. The logic state of the pin will determine the operation of the device. For example, the PAR/SER digital pin will determine if the communication is in parallel or serial mode. These pins are automatically controlled by the PHI digital controller when the GUI is in "hardware mode". The logic level on these pins can be monitored using test points on J11 or as shown in Figure 3-2. Some of these digital control pins also have resistors that can be used to configure the logic levels when the PHI controller is not used. Figure 3-2 shows the static logic configuration. To set a pin to logic high the resistor connected to DVDD is installed. To set an input to logic low the resistor connected to GND needs to be installed. It is important to understand that the configuration of these resistors does not matter when the PHI is used as it will drive the logic level to whatever the GUI setting is. These digital input configuration resistors only matter when the EVM is disconnect from the PHI and used with a different digital controller.

Figure 3-2 also shows the operation of the reset control line. This reset can be initiated by the PHI controller or by the push button switch. Note that RESET is an active high signal so the two reset signals are applied to an OR function so that the device will be reset if either the push button is pressed or the PHI drives the signal active high.

Figure 3-2 Static Digital Input Configuration