SBAU269C October   2016  – August 2021 ADS8900B

 

  1.   Trademarks
  2. 1EVM Overview
    1. 1.1 ADS8900EVM-PDK Kit Features
    2. 1.2 ADS8900EVM Features
  3. 2Analog Interface
    1. 2.1 ADS8900B Connections and Decoupling
    2. 2.2 ADC Amplifier Input Drive
    3. 2.3 Voltage Reference and VCM Scaling
  4. 3Digital Interface
    1. 3.1 multiSPI™ for ADC Digital I/O
    2. 3.2 I2C Bus for Onboard EEPROM
  5. 4Power Supplies
    1. 4.1 Positive Supply and Test Points
    2. 4.2 Negative Supply
  6. 5ADS8900EVM-PDK Initial Setup
    1. 5.1 Software Installation
    2. 5.2 Default Jumper Settings for Differential Inputs
    3. 5.3 Default Jumpers for Bipolar, Single-Ended Inputs
    4. 5.4 Default Jumpers for Unipolar, Single-Ended Inputs
    5. 5.5 External Source Requirements for ADS8900 Evaluation
  7. 6ADS8900EVM-PDK Operation
    1. 6.1 EVM GUI Global Settings for ADC Control
    2. 6.2 Register Map Configuration Tool
    3. 6.3 Time Domain Display Tool
    4. 6.4 Spectral Analysis Tool
    5. 6.5 Histogram Tool
    6. 6.6 Linearity Analysis Tool
    7. 6.7 ADS8900BEVM Support for ADS8910B and ADS8920B Devices
  8. 7Bill of Materials, PCB Layout, and Schematics
    1. 7.1 Bill of Materials (BOM)
    2. 7.2 PCB Layout
    3. 7.3 Schematics
  9. 8Revision History

3.1 multiSPI™ for ADC Digital I/O

The ADS8900BEVM-PDK supports all interface modes, as detailed in the ADS8900B data sheet. In addition to the standard SPI modes (with single-, dual- and quad-SDO lanes), the multiSPI modes support single- and dual-data output rates and the four possible clock source settings as well. The PHI is capable of operating at a 1.8-V logic level and is directly connected to the digital I/O lines of the ADC.