SBAU345A March   2020  – May 2022 PCM1840

 

  1. 1PCM1840 Evaluation Module
    1.     Trademarks
  2. 1Introduction
  3. 2Power Supply
  4. 3Hardware Configuration
    1. 3.1 PCM1840EVM Inputs
      1. 3.1.1 Line Inputs
      2. 3.1.2 Onboard Microphone Input
  5. 4EVM Overview
  6. 5Layer Plots
  7. 6Schematic and Bill of Materials
    1. 6.1 PCM1840EVM Schematic
    2. 6.2 PCM1840EVM Bill of Materials
  8. 7Related Documentation
  9. 8Revision History

3 Hardware Configuration

The format of the audio data and the operating mode of the ADC are controlled by the following pins: MD0, MD1, MSZ, FMT0, and FMT1. These signals are referenced to IOVDD and can be set to high (1) or low (0). If no shunt is installed, then a 10-kΩ pulldown resistor will set the pin low so that the ADC remains in a defined state. Table 3-1 shows the header numbers and their pin functions and Table 3-2 shows the possible modes and output formats. The MSZ pin selects whether the device is a master or a slave on the audio bus. When MSZ is pulled high, the device is in slave mode and MD1 becomes an input for MCLK. A shunt connecting J19 to the center pin of J18 will route the MCLK signal provided on J8 to the MD1 pin on the ADC to allow for easy interfacing with audio measurement equipment.

Table 3-1 PCM1840 EVM Headers and Jumpers
Designator Function
J1 Differential line, microphone input 1
J2 Differential line, microphone input 2
J3 Differential line, microphone input 3
J4 Differential line, microphone input 4
J5 IOVDD-SYS voltage selection (1.8 V or 3.3 V)
J6 +5-V supply input
J7 Connector to AC-MB
J8 Digital audio serial interface
J9 Connect AVDD to onboard 3.3-V regulator
J10 Connect IOVDD to IOVDD-SYS
J13 MSZ select
J14 Connect MICBIAS to onboard microphone
J15 Microphone OUT+ to ADC IN1P
J16 Microphone OUT– to ADC IN1M
J17 MDO select
J18 MD1 select
J19 Connect MCLK to MD1
J20 FMT0 select
J21 FMT1 select
Table 3-2 PCM1840 Hardware Controllable Settings
MD0 Modes
MD0 MSZ (0 = Slave, 1 = Master) MDO Functional Mode
0 0 Linear phase filter
0 1 MCLK = 256 × Fs
1 0 Low latency filter
1 1 MCLK = 512 × Fs
MD1 Modes
MD1 MSZ (0 = Slave, 1 = Master) MD1 Functional Mode
0 0 DRE disabled
0 1 MCLK input
1 0 DRE enabled
1 1 MCLK input
Audio Output Data Format
FMT0 FMT1 Data Format
0 0 4 channel TDM
0 1 2 channel TDM
1 0 2 channel left-justified
1 1 2 channel I2S

All hardware pins are tied low by default, placing the device in slave mode with a linear phase filter, DRE disabled, and 4-channel TDM audio output.

For more information on the operating modes of the PCM1840 device, see the PCM1840 Quad Channel, 32-Bit, 192-kHz, Burr-Brown™ Audio ADC Data Sheet.