SBAU345A March   2020  – May 2022 PCM1840

 

  1. 1PCM1840 Evaluation Module
    1.     Trademarks
  2. 1Introduction
  3. 2Power Supply
  4. 3Hardware Configuration
    1. 3.1 PCM1840EVM Inputs
      1. 3.1.1 Line Inputs
      2. 3.1.2 Onboard Microphone Input
  5. 4EVM Overview
  6. 5Layer Plots
  7. 6Schematic and Bill of Materials
    1. 6.1 PCM1840EVM Schematic
    2. 6.2 PCM1840EVM Bill of Materials
  8. 7Related Documentation
  9. 8Revision History

Power Supply

The PCM1840EVM can be powered with a single 5-V power supply connected to J6. Onboard low dropout regulators convert the 5-V supply to the 3.3-V and 1.8-V rails used by the ADC. The analog supply, AVDD, is fixed at 3.3 V. The digital supply, IOVDD, can be set to either 1.8 V or 3.3 V with J5. It is also possible to power the ADC directly by removing J9 and J5 and applying a voltage directly to the AVDD and IOVDD test points. Note that if this is done, it is important to keep J10 populated (or ensure there is a path between the pins if the supply current is being monitored) as this jumper connects the applied IOVDD to the mode selection pins and other circuitry that relies on IOVDD. If external supplies are used, there is an onboard voltage supervisor, U3, that will hold the ADC in shutdown until both AVDD and IOVDD have reached their respective threshold voltages. The shutdown thresholds for the supply voltages can be adjusted as shown in Equation 1 and Equation 2. The supervisor can also be removed from the shutdown logic by depopulating R5. For more information on the reset supervisor, see the TPS37xx Dual-Channel, Low-Power, High-Accuracy Voltage Detectors Data Sheet.

Equation 1. GUID-A0989F5E-7ABE-4BD9-9481-A7CC4BB56CEA-low.gif
Equation 2. GUID-F87860D6-9888-4E67-B4D6-502AE5B6A978-low.gif