SBAU351 April   2021

 

  1.   Trademarks
  2. 1EVM Overview
    1. 1.1 ADS127L11EVM Kit
    2. 1.2 ADS127L11EVM Board
    3. 1.3 ADS127L11EVM-PDK-GUI Unsupported Features
  3. 2EVM Analog Interface
    1. 2.1 EVM Analog Input Options
    2. 2.2 ADC Connections and Decoupling
    3. 2.3 ADC Input Drive Amplifiers
    4. 2.4 VCOM Buffer
    5. 2.5 Onboard Voltage Reference
    6. 2.6 External Voltage Reference
    7. 2.7 Clock Tree
  4. 3Digital Interface
    1. 3.1 Serial Interface (SPI)
    2. 3.2 I2C Bus for Onboard EEPROM
  5. 4Power Supplies
    1. 4.1 Power Connection and Configuration
    2. 4.2 Low Dropout Regulator (LDO)
  6. 5ADS127L11EVM Software Installation
  7. 6EVM Operation
    1. 6.1 Connecting the Hardware
    2. 6.2 Optional Connections to the EVM
    3. 6.3 EVM GUI Global Settings for ADC Control
    4. 6.4 Time Domain Display
    5. 6.5 Frequency Domain Display
    6. 6.6 Histogram Display
  8. 7Bill of Materials, Schematics, and Layout
    1. 7.1 Bill of Materials
    2. 7.2 Board Layouts
    3. 7.3 Schematics
  9. 8References

4.2 Low Dropout Regulator (LDO)

Figure 4-2 shows how the 5.5-V power from the PHI is regulated to 5 V using a low-noise TPS7A4700 LDO. By default, the shunt on (JP4) 1-2 routes 5.5 V from the PHI to the LDO. The 5-V LDO can also be supplied by external power on J12 by moving the shunt on (JP4) to position 2-3. The 5-V LDO output is used for the AVDD connections and can be reprogrammed to different output voltages using R72, R73, R75, R78, R82, and R83.

There is an additional LDO that generates –2.5 V for AVSS, using the low-noise TPS7A3001 LDO. This LDO is only supplied by external power on J12. By default, AVSS is connected to GND with a shunt on (JP5) 1-2. If AVSS must be set to –2.5 V, then connect an external negative supply to J12 and move the shunt on (JP5) to position 2-3.

GUID-20210331-CA0I-FTH9-XS2G-0SL0MG03S39B-low.svgFigure 4-2 5.5 V to 5 V LDO