SBAU353 October   2021

 

  1.   Trademarks
  2. 1EVM Overview
    1. 1.1 ADS131A04EVM Kit
    2. 1.2 ADS131A04EVM Board
  3. 2ADS131A04EVM Quick Start Guide
  4. 3EVM Analog Interface
    1. 3.1 ADC Analog Input Signal Path
    2. 3.2 ADC External Clock (XTAL1/CLKIN and XTAL2) Options
  5. 4Digital Interface
    1. 4.1 SPI Communication
    2. 4.2 Connection to the PHI
    3. 4.3 Digital Header
    4. 4.4 LaunchPad Connectors
  6. 5Power Supplies
  7. 6ADS131A04EVM Initial Setup
    1. 6.1 Default Jumper Settings
    2. 6.2 EVM Graphical User Interface (GUI) Software Installation
  8. 7ADS131A04EVM Software Reference
    1. 7.1 EVM GUI Global Settings for ADC Control
    2. 7.2 Register Map Configuration Tool
    3. 7.3 Time Domain Display Tool
    4. 7.4 Spectral Analysis Tool
    5. 7.5 Histogram Tool
  9. 8ADS131A04EVM Bill of Materials, PCB Layout, and Schematic
    1. 8.1 Bill of Materials
    2. 8.2 PCB Layout
    3. 8.3 Schematic
  10. 9References

3.2 ADC External Clock (XTAL1/CLKIN and XTAL2) Options

Multiple clocks are created from one external main clock source in the ADS131A04 to create device configuration flexibility. The ADC operates from the internal system clock, ICLK, which is provided in one of three ways.

  • A crystal oscillator can be applied between XTAL1/CLKIN and XTAL2, generating a main clock to be divided down using the CLK_DIV[2:0] bits in the CLK1 register to generate ICLK.
    • The onboard crystal oscillator (Y1) provides the nominal 16.384-MHz clock frequency.
    • This is the default configuration for the EVM.
  • An external main clock, CLKIN, can be applied directly to the XTAL1/CLKIN pin to be divided down to generate ICLK using the CLK_DIV[2:0] bits in the CLK1 register.
    • In this case, remove R29 and R30 to disconnect the crystal oscillator and use JP4 to provide an external clock. Pin 1 of JP4 is the CLKIN node where pin 2 of JP4 is GND.
    • Be sure to review the valid CLKIN input frequency in the datasheet when IOVDD is above 2.7 V (16.384-MHz typical) or below 2.7 V (8.192-MHz typical).
  • A free-running SCLK can be internally routed to be set as ICLK. This mode is only available in synchronous peripheral SPI interface mode. Tie the CLKIN/XTAL1 pin to GND.
    • To tie the CLKIN/XTAL1 pin to GND, cover JP4 1x2, 100 mil header with a jumper.
    • Note this interface mode is not compatible with the provided EVM software.
Figure 3-3 XTAL1/CLKIN and XTAL2 Clock (Schematic)

The hardware changes are described in Table 3-2.

Table 3-2 Clock Source Options for XTAL1/CLKIN and XTAL2
Clock Source Option Hardware Description
An external main clock Uninstall R29 and R30, use JP4 pin 1 for the CLKIN signal and JP4 pin 2 for GND
A crystal oscillator

(Default)

 Ensure R29, R30, and Y1 are populated
A free-running SCLK Install jumper onto JP4 to connect XTAL1/CLKIN to GND