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The ADC3664EVM is an evaluation board used to evaluate the ADC3664 analog-to-digital converter (ADC) from Texas Instruments. The ADC3664EVM is a dual-channel, 14-bit ADC that can operate up to 125 Mega-samples per second (MSPS). The ADC3664 uses a serial LVDS (SLVDS) interface to output the digital data. The SLVDS interface supports output rates to ~1 Gbps. The ADC3664 can be operated in 'oversampling + decimating' mode using the internal decimation filter in order to improve the dynamic range and relax external anti-aliasing filter.
The ADC3664EVM is equipped with the following features:
Power over mini-USB
By default, the EVM is configured to receive external inputs for the sampling clock and analog input via AC-coupled, transformer (balun) inputs. These transformers perform single-ended to differential conversion, and provide a low noise/distortion passive input.
To exercise the full performance capabilities of this high performance SAR ADC, it is recommended to evaluate the ADC in the default configuration, and then evaluate in other configurations (like utilizing the FDA input), as required.
This hardware setup procedure is written with the intent to use external clocking (sample clock and DCLKIN) and transformer coupled analog inputs. Using onboard FDA driven analog inputs is an option, and instructions are provided toward the end of this document to make the required hardware/software modifications.
The ADC3664EVM receives power from the USB 2.0, +5 V rail, and is then converted to +3.3 VDC and +1.8 VDC. The ADC receives +1.8 VDC from the TPS62231 DC-DC converter. The power consumption of the 1.8 V rail can be monitored (using the INA226) in the ADC35xxEVM GUI. USB-to-SPI communication is established using the FTDI (FT4234H). The ADC clocks are supplied externally, and have limited functionality for the onboard CDCE6214 (Decimation modes only). The ADC3664 analog input can be AC coupled through the Balun (ADT1-6T+) input, or DC (or AC) coupled with the onboard FDA (THS4541). The analog input is 3.2 Vpp, and is driven a -1 dBFS (~2.8 Vpp) in all examples in this user's guide.
The ADC3664 has a +1.6 V voltage reference (VREF), and can be supplied internally or externally. By default, the EVM is configured to supply an external voltage reference using the REF3318 (divided down to +1.6V) and the OPA837 high speed amplifier to drive the voltage reference. At any time, the VREF can be changed to internal reference by SPI write.
The ADC3664 family uses an unbuffered analog input, so a glitch filter is required to attenuate the ADC sampling glitch from when the sampling capacitors switch (sample/hold). The glitch filter acts as a low pass filter with an corner frequency (Fc) at 30 MHz (accepts DC to 30 MHz). The Fc of the glitch filter can be modified by changing filter components.
The ADC3664EVM LVDS output data is routed to an FMC connector, and then connected to the LVDS Interposer card. This interposer card then maps to the TSW1400EVM's HSMC connector in order to capture the ADC36XXEVM SLVDS clock and data signals.
Ensure that jumper J16 is shunted in the 2-3 position. This allows 5 V to be supplied to the ADC3664EVM through the mini-USB connector.
If an external 5-V supply is desired, J16 must be shunted in the 1-2 position, and the external 5 V can be connected to the test point labeled "+5 EXT". The USB data connection will still be connected for SPI communications.
J13 is tied to the REFBUF pin. It can be left floating, or can be tied to 1.8 V (shunt pins 2-3) for normal operation.
J14 is tied to the PDN/SYNC pin. It can be left floating for tied to ground (shunt pins 1-2) for normal operation. To power down the ADC, tied to 1.8 V (shunt pins 2-3). The ADC may also be powered down via SPI.
The following equipment is included in the EVM evaluation kit:
The following equipment is not included in the EVM evaluation kit, but is required for evaluation of this EVM:
TI recommends the following generators:
A bandpass filter is required for the analog input signal due to most signal generators addition of phase noise or spurious components. A bandpass filter should also be used for the sample clock input. The DCLKIN input does not require a bandpass filter. If bandpass filters are not used, then the true performance of the ADC may not be seen clearly, and will be limited by the performance of the signal generators being used.
The following recommended bandpass filter will have: