SBAU378A September   2021  – January 2022 ADS1148 , ADS1248

 

  1.   Trademarks
  2. 1Introduction
  3. 2Getting Started With the ADS1x48EVM
  4. 3ADS1x48EVM Overview
    1. 3.1 Analog and Digital Power Supplies
    2. 3.2 Voltage Reference Options
    3. 3.3 Clock Options
    4. 3.4 Digital Interface
    5. 3.5 Analog Input Connections
      1. 3.5.1 Connecting a Thermocouple to J5 on the ADS1x48EVM
      2. 3.5.2 Connecting a Thermistor to J5 on the ADS1x48EVM
        1. 3.5.2.1 Using Thermistor RT1 for Thermocouple Cold Junction Compensation
      3. 3.5.3 Connecting an RTD to J6 on the ADS1x48EVM
        1. 3.5.3.1 Connecting a 2-Wire RTD Using a Low-Side RREF to J6 on the ADS1x48EVM
        2. 3.5.3.2 Connecting a 2-Wire RTD Using a High-Side RREF to J6 on the ADS1x48EVM
        3. 3.5.3.3 Connecting a 3-Wire RTD Using One IDAC and a Low-Side RREF to J6 on the ADS1x48EVM
        4. 3.5.3.4 Connecting a 3-Wire RTD Using One IDAC and a High-Side RREF to J6 on the ADS1x48EVM
        5. 3.5.3.5 Connecting a 3-Wire RTD Using Two IDACs and a Low-Side RREF to J6 on the ADS1x48EVM
        6. 3.5.3.6 Connecting a 3-Wire RTD Using Two IDACs and a High-Side RREF to J6 on the ADS1x48EVM
        7. 3.5.3.7 Connecting a 4-Wire RTD Using a Low-Side RREF to J6 on the ADS1x48EVM
        8. 3.5.3.8 Connecting a 4-Wire RTD Using a High-Side RREF to J6 on the ADS1x48EVM
        9. 3.5.3.9 Summary of ADS1x48EVM RTD Configuration Settings
      4. 3.5.4 Connecting a General-Purpose Input to J5 on the ADS1x48EVM
  5. 4ADS1x48EVM GUI
    1. 4.1 Home
      1. 4.1.1 Menu Bar
        1. 4.1.1.1 File Menu
        2. 4.1.1.2 Options Menu
        3. 4.1.1.3 Tools Menu
        4. 4.1.1.4 Help Menu
    2. 4.2 Data Capture
      1. 4.2.1 Time Domain and Histogram Statistics
      2. 4.2.2 Time Domain Plot
      3. 4.2.3 Histogram Plot
      4. 4.2.4 FFT Statistics and Plot
    3. 4.3 Register Map
      1. 4.3.1 Register Read and Write Options
        1. 4.3.1.1 Read Register Options
        2. 4.3.1.2 Write Register Options
  6. 5Bill of Materials, Printed Circuit Board Layout, and Schematic
    1. 5.1 Bill of Materials
    2. 5.2 Printed Circuit Board Layout
    3. 5.3 Schematic
  7. 6Revision History

4.2.1 Time Domain and Histogram Statistics

The Time Domain and Histogram plots share the same statistical information shown in Figure 4-7:

  • Input Channels selected
  • Min code within the data set
  • Max code within the data set
  • Mean code value within the data set
  • Std Dev representing the standard deviation within the data set
  • Pk-to-Pk representing the total noise peak-to-peak within the data set
  • Eff. Res representing the effective resolution as number of bits with the value in parenthesis showing the noise-free number of bits
GUID-20210706-CA0I-CGXC-8GZB-VVLQ9F24K6Z2-low.pngFigure 4-7 Capture Statistics