SBAU383A June   2021  – February 2022 BUF802

 

  1.   Trademarks
  2. Introduction
  3. Configuration and Usage
  4. Power Connections
  5. Input and Output Connections
  6. Stand-Alone Buffer Configuration
  7. Composite Loop Configuration
  8. External Clamping
  9. Schematic
  10. Layout Prints
  11. 10Related Documentation
  12. 11Revision History

Layout Prints

Figure 9-1 through Figure 9-8 show the PCB layers for the BUF802RGTEVM standalone circuit and composite circuit respectively.

GUID-20220204-SS0I-CKLP-QKMZ-XBM7QZMRGVV0-low.pngFigure 9-1 Standalone Configuration Top Layers
GUID-20220204-SS0I-TBGN-NSWR-74MVXQF1TJHS-low.pngFigure 9-3 Standalone Configuration Power Layer
GUID-20220204-SS0I-M1QC-N5VC-DWTXNRHB8SWT-low.pngFigure 9-5 Composite Configuration Top Layers
GUID-20220204-SS0I-KCLB-HJTB-QG1FK9LFNGXZ-low.pngFigure 9-7 Composite Configuration Power Layer
GUID-20220204-SS0I-PK59-LNRQ-6FXP5DRNDNTC-low.pngFigure 9-2 Standalone Configuration Ground Layer
GUID-20220204-SS0I-GQQ5-4NBS-HHCT2FDQF6XX-low.pngFigure 9-4 Standalone Configuration Bottom Layers
GUID-20220204-SS0I-8XKR-HVQK-JH3VKDC5LXQT-low.pngFigure 9-6 Composite Configuration Ground Layer
GUID-20220204-SS0I-LHJ7-GNFV-0LLZNT9XNZDC-low.pngFigure 9-8 Composite Configuration Bottom Layers