SBAU394A April   2022  – September 2022

 

  1.   ADS1285 Evaluation Module
  2.   Trademarks
  3. 1 EVM Overview
    1. 1.1 ADS1285EVM-PDK Kit
  4. 2 ADS1285EVM-PDK Quick-Start Guide
  5. 3 EVM Analog Interface
    1. 3.1 ADC Analog Input Signal Path
    2. 3.2 ADC Input Clock (CLK) Options
  6. 4 Digital Interface
    1. 4.1 Connection to the PHI
    2. 4.2 Digital Header
  7. 5 Power Supplies
  8. 6 Digital-to-Analog Converter
  9. 7 ADS1285EVM-PDK Initial Setup
    1. 7.1 Default Jumper Settings
    2. 7.2 EVM Graphical User Interface (GUI) Software Installation
  10. 8 ADS1285EVM-PDK Software Reference
    1. 8.1 EVM GUI Global Settings for ADC Control
    2. 8.2 Register Map Configuration Tool
    3. 8.3 Time Domain Display Tool
    4. 8.4 Spectral Analysis Tool
    5. 8.5 Histogram Tool
    6. 8.6 DAC Configuration Tool
  11. 9 ADS1285EVM-PDK Bill of Materials, PCB Layout, and Schematics
    1. 9.1 Bill of Materials
    2. 9.2 PCB Layout
    3. 9.3 Schematics
  12. 10References
  13. 11Revision History

5 Power Supplies

The PHI provides multiple power-supply options for the EVM, derived from the USB supply of the computer that is routed to the 5.5-V net on the ADS1285EVM-PDK on the board.

The EEPROM on the ADS1285EVM-PDK uses a 3.3-V power supply, ID_PWR, generated directly by the PHI. The 3.3-V supply to the digital section of the ADC (3V3_IOVDD) is provided directly by a separate LDO on the PHI.

Figure 5-1 and Table 5-1 describe the supply generation and programmable configurations, respectively.

GUID-20220913-SS0I-GGNX-XHP9-LCPS0T9Z3XK6-low.gif Figure 5-1 ADS1285EVM-PDK AVDD1, AVDD2, and AVSS+5V Supply Generation (Schematic)
Table 5-1 Programmable LDO Configurations
VOUT (V)(2) 3P2V 1P6V 0P8V 0P4V 0P2V 0P1V
2.5 — — Installed(1) — Installed Installed
3.0 — Installed — — — —
3.3 — Installed — — Installed Installed
4.5 — Installed Installed Installed Installed Installed
5.0 Installed — — Installed — —
(1) Installed = Solder a 0-Ω jumper to GND/AVSS.
(2) VOUT = 1.4 V + Σ (all grounded pins).

The PGA positive analog supply of the ADC, AVDD1, is powered by the TPS7A4701 or TPS7A4700 (U2) onboard the EVM, which is a low-noise linear regulator that uses the 5.5-V supply on the PHI to generate a cleaner 5-V output. The TPS47A470x is a configurable LDO so R8 to R13 can be used to change the voltage.

AVDD2 is the modulator analog supply that is also used by the ADC. As with AVDD1, AVDD2 is generated by the TPS7A470x (U3) onboard the EVM, which is a low-noise linear regulator that uses the 5.5-V supply on the PHI to generate a cleaner 5-V output. The TPS7A470x is a configurable LDO so R14 to R19 can be used to change the voltage but a lower AVDD2 will result in lower THD performance in unipolar mode.

AVSS+5V is used for the analog supply of the DAC1282. This pin also uses a TPS7A470x (U4) onboard the EVM, which is a low-noise linear regulator that uses the 5.5-V supply on the PHI to generate a cleaner 5-V output. The DAC1282 requires a 5-V supply so R20 to R25 must not be modified.

The user has the option to configure the EVM for unipolar supplies (AVSS = 0 V) by placing a jumper to cover pins 1 and 2 of J4 (UNIPOL), or to configure the EVM for bidirectional supplies (AVSS = –2.5 V) by placing the jumper to cover pins 2 and 3 of J4 (BIPOL). The TPS7A3001 (U5) is an LDO with a VIN range from –3 V to –36 V that provides a clean –2.5-V output for the AVSS voltage. However, an external voltage is needed to supply the AVSS voltage, which can be supplied using J3. Because AVDD1 is referenced to AVSS, the output AVDD1 must be modified using R8 to R13 so that the AVDD1 to AVSS voltage does not go above the recommended operating conditions. Figure 5-2 shows the supply selection and –2.5-V generation circuit.

GUID-20220830-SS0I-3MHF-CQK5-4DBVKHHMGCWV-low.gif Figure 5-2 ADS1285EVM-PDK Unipolar and Bidirectional Supplies Selection (Schematic)

AVDD1 is used as the supply for the REF6241, which is a high-precision voltage reference with an integrated high-bandwidth buffer in reference to AVSS. The voltage reference can be used to supply the positive reference, VREFP, for the ADC and DAC using R38 as a pass transistor. Alternatively, R38 and R42 can be depopulated so the positive and negative reference externally using pins 1 and 2 of J10, respectively.

Figure 5-3 shows a schematic of the voltage reference.

GUID-20220830-SS0I-KBJX-C1ZH-RMQT3DCZ8MJL-low.gif Figure 5-3 Voltage Reference (Schematic)

The power supply for each active component on the EVM is bypassed with a ceramic capacitor placed close to that component. Additionally, the EVM layout uses thick traces or large copper fill areas, where possible, between bypass capacitors and their loads to minimize inductance along the load current path.

As mentioned previously in Section 1, power to the EVM is supplied by the PHI through connector J5. For information about PHI pins and the power connections, see Table 4-1.

With modifications, the user can use external supplies for any voltage supplies. Using the ADC PWR header (J26), DAC PWR header (J1), and the unipolar or bipolar select (J4); the shunts can be depopulated for direct access to the AVDD1, AVDD2, AVSS+5V, DVDD, and AVSS pins.