SBAU394A April   2022  – September 2022

 

  1.   ADS1285 Evaluation Module
  2.   Trademarks
  3. 1 EVM Overview
    1. 1.1 ADS1285EVM-PDK Kit
  4. 2 ADS1285EVM-PDK Quick-Start Guide
  5. 3 EVM Analog Interface
    1. 3.1 ADC Analog Input Signal Path
    2. 3.2 ADC Input Clock (CLK) Options
  6. 4 Digital Interface
    1. 4.1 Connection to the PHI
    2. 4.2 Digital Header
  7. 5 Power Supplies
  8. 6 Digital-to-Analog Converter
  9. 7 ADS1285EVM-PDK Initial Setup
    1. 7.1 Default Jumper Settings
    2. 7.2 EVM Graphical User Interface (GUI) Software Installation
  10. 8 ADS1285EVM-PDK Software Reference
    1. 8.1 EVM GUI Global Settings for ADC Control
    2. 8.2 Register Map Configuration Tool
    3. 8.3 Time Domain Display Tool
    4. 8.4 Spectral Analysis Tool
    5. 8.5 Histogram Tool
    6. 8.6 DAC Configuration Tool
  11. 9 ADS1285EVM-PDK Bill of Materials, PCB Layout, and Schematics
    1. 9.1 Bill of Materials
    2. 9.2 PCB Layout
    3. 9.3 Schematics
  12. 10References
  13. 11Revision History

7.1 Default Jumper Settings

After unpacking, the EVM is already configured with the default jumper settings. Figure 7-1 shows the locations for the default jumpers and Table 7-1 shows the functions of the default shunts.

GUID-20220829-SS0I-8F5S-VGVM-7TLLCLHG9SXF-low.jpgFigure 7-1 ADS1285EVM-PDK Jumper Default Settings
Table 7-1 Default Shunt Settings
Header DesignatorPositionFunction
J11[1-2]Enables the REF62x supply to VREFP
J4[1-2]Connects AVSS to GND for unipolar ADC supply mode
J7[3-4]Connects CLK to an 8.192-MHz source from the crystal oscillator
J10Not installedHeader to supply the external reference voltage to VREFN and VREFP
J1[1-2]DAC PWR: Connects the output of the U4 LDO (AVSS+5V) to the DAC analog supply pin (AVDD)
J1[3-4]DAC PWR: Connects the PHI digital supply (DVDD) to the DAC digital supply pin (DVDD)
J15[1-2]ADC PWR: Connects the output of the U2 LDO (AVDD1) to the ADC analog supply 1 (AVDD1)
J15[3-4]ADC PWR: Connects the output of the U3 LDO (AVDD2) to the ADC analog supply 2 (AVDD2)
J15[5-6]ADC PWR: Connects the PHI digital supply (DVDD) to the ADC digital supply (IOVDD)
J3Not installedHeader to supply the external input to U5 for the –2.5-V supply
J8Not InstalledEnables 8.192-MHz crystal oscillator

Table 7-2 lists the nominal voltages that result from the default configuration.

Table 7-2 Nominal Voltages Resulting From a Default Configuration
Supply NameVoltage (Referenced to GND)
AVSSGND (0 V)
AVSS+5V5 V
DVDD (IOVDD)3.3 V
AVDD15 V
AVDD25 V
5.5V5.5 V
REFP4.096 V
–2.5VNA, external supply needed to generate –2.5 V