SBAU395 april   2023 DAC39RF10

 

  1.   Introduction
  2. 1Trademarks
  3. 2Required Equipment
  4. 3Setup Procedure
    1. 3.1  Installing the High Speed Data Converter (HSDC) Pro Software
    2. 3.2  Installing the DAC39RF10EVM Configuration GUI Software
    3. 3.3  Connect the DAC39RF10EVM and TSW14J59EVM
    4. 3.4  Connect the Power Supplies to the Boards (Power Off)
    5. 3.5  Connect the Spectrum Analyzer to the EVM
    6. 3.6  Turn On the TSW14J59EVM Power and Connect to the PC
    7. 3.7  Turn On the DAC39RF10EVM Power Supplies and Connect to the PC
    8. 3.8  Turn On the Signal Generator RF Outputs
    9. 3.9  Launch the DAC39RF10EVM GUI and Program the DAC EVM
    10. 3.10 Programming the NCO
      1. 3.10.1 SPIDAC( NCO only) Operation
    11. 3.11 Launch the HSDCpro Software and Load the FPGA Image to the TSW14J59EVM
  5. 4Device Configuration
    1. 4.1 Supported JESD204C Device Features
    2. 4.2 Tab Organization
    3. 4.3 Register Map and Console Control
  6. 5Troubleshooting the DAC39RF10EVM
  7. 6References
    1. 6.1 Technical Reference Documents
    2. 6.2 TSW14J59EVM Operation
  8. 7Appendix
    1. 7.1 Customizing the EVM for Optional Clocking Support
      1. 7.1.1 LMX->DACCLK | LMX/LMK-> FPGA option (Default)
      2. 7.1.2 EXT->DACCLK | LMX/LMK-> FPGA Clocking Option
      3. 7.1.3 EXT->DACCLK | LMK-> FPGA Clocking Option
    2. 7.2 Signal Routing
    3. 7.3 Analog Outputs
    4. 7.4 Jumpers and LEDs

4.1 Supported JESD204C Device Features

The DAC device supports some configuration of the JESD204C interface. Due to limitations in the TSW14J59EVM firmware, all JESD204C link features of the DAC device are not supported. Table 4-1 lists the supported and non-supported features.

Table 4-1 Supported and Non-Supported Features of the JESD204C Device
JESD204C Feature Supported by DAC Device Supported by TSW14J59EVM
Number of lanes per link (L) L = 1, 2, 3, 4, 6, 8,12,16(1) L = 1, 2, 3, 4, 6, 8,12,16 supported
Scrambling Supported Supported
Test patterns PRBS7, PRBS9, PRBS15, PRBS31 Not Supported
Speed Lane rates from 0.75 to 12.8 Gbps Lane rates from 2 to 17.16 Gbps
ƒ(SAMPLE) parameter must be properly set in HSDC Pro GUI.
(1) Dependent on bypass or decimation mode and output rate selection. Always disable the JESD204 block before changing any of the JESD204C settings. Once the settings are changed, re-enable the JESD204 block.