The AMC131M03 requires a continuous, free-running external controller clock at the CLKIN pin for normal operation. The onboard complementary metal oxide semiconductor (CMOS) crystal oscillator (Y1) provides the nominal 8.192-MHz clock frequency used in the high-resolution (HR) mode of the device. A D flip-flops (U3) divide the Y1 clock output to produce clock frequencies of 4.096 MHz to support the low-power (LP) mode.

Install a jumper in the appropriate position on the JP4 header to provide four selectable clock frequency options. An external clock frequency can also be provided to any odd-numbered pin on JP4 when the jumper is uninstalled. TI also recommends powering down Y1 by installing JP6 when providing an external clock. When using an external clock, ground must be shared between the external clock source and the EVM ground. The external clock must adhere to the frequency and amplitude limits outlined in the AMC131M03 data sheet. Table 2-1 lists the JP4 jumper settings for the clock input selections.

Figure 2-2 Clock Tree (Schematic)