SBAU413A october   2022  – may 2023

 

  1.   Abstract
  2.   Trademarks
  3. 1EVM Overview
    1. 1.1 ADS131B26Q1EVM-PDK Features
    2. 1.2 ADS131B26Q1EVM-PDK Quick-Start Guide
  4. 2Analog Interface
    1. 2.1 Terminal Blocks and Test Points
    2. 2.2 ADC1A and ADC1B
    3. 2.3 ADC2A and ADC2B
    4. 2.4 ADC3A and ADC3B
  5. 3Digital Interface
    1. 3.1 Connection to the PHI Controller
    2. 3.2 Digital Header
    3. 3.3 Clock Options
  6. 4Power Supplies
    1. 4.1 DC/DC Converter Circuit
    2. 4.2 ADC Power Supplies
    3. 4.3 Power Supply and Voltage Reference Decoupling
  7. 5ADS131B26Q1EVM-PDK Initial Setup
    1. 5.1 Default Jumper Settings
    2. 5.2 EVM Graphical User Interface (GUI) Software Installation
  8. 6ADS131B26Q1EVM-PDK Software Reference
    1. 6.1 Global Settings for ADC Control
    2. 6.2 Register Map Configuration
      1. 6.2.1 Register Map Basics
      2. 6.2.2 ADC1A, ADC3A and ADC1B, ADC3B Configuration
      3. 6.2.3 ADC2A and ADC2B Configuration
    3. 6.3 Analysis Tools
      1. 6.3.1 Time Domain Display
      2. 6.3.2 Spectral Analysis Tool
      3. 6.3.3 Histogram Analysis
      4. 6.3.4 Sequencer Analysis
  9. 7ADS131B26Q1EVM-PDK Bill of Materials, PCB Layout, and Schematics
    1. 7.1 Bill of Materials (BOM)
    2. 7.2 PCB Layout
    3. 7.3 Schematics
  10. 8Revision History

6.2.2 ADC1A, ADC3A and ADC1B, ADC3B Configuration

Figure 6-3 displays the Channel Configurations register map page. These register controls allow the user to configure the register settings for ADC1A, ADC1B, ADC3A, and ADC3B in a more user-friendly interface.

The page is partitioned into ADC1A and ADC3A settings on the left and ADC1B and ADC3B settings on the right. At the top of each section are Global Settings for ADC1A and ADC3A and Global Settings for ADC1B and ADC3B, which contain the register settings from addresses 82h and C2h, respectively.

Below the global channel settings are individual ADC controls to figure the following settings:

  • ADC enable
  • Channel gain
  • Channel Mux
  • Current Source or Sink Mux
  • Current Source or Sink Value
  • Offset Calibration
  • Gain Calibration

GUID-20220922-SS0I-2KLB-B70F-XSM973PPP0J7-low.svgFigure 6-3 Channel Configurations Register Page