As mentioned previously in Section 1, power to the EVM can be supplied entirely by the PHI controller through connector J9. For information about the PHI pins and power connections, see Table 3-1.

A 3.3-V LDO output on the PHI (ISO_3V3) is used to power the controller side of the isolation barrier, including the digital isolators, onboard 8.192-MHz oscillator, and D flip-flop clock divider circuit. ISO_3V3 is also the default option to power the transformer driver (SN6505B-Q1, U6) and generate the supplies used on the ADC side of the isolation barrier. U6 can also be powered by the raw USB supply (EVM_RAW_5V) by uninstalling R96 and installing R97.

By default, the SN6505B-Q1 uses an internal 420-kHz clock to set the transformer switching frequency. This clock operates asynchronously to the ADS131B26-Q1 internal clock (CLK = 8.192 MHz). However, the EVM also supports an external ADC clock, which can be provided either by enabling the onboard oscillator (Y1) or by connecting a clock from an external source to the onboard SMA connector (J10). When an external clock is used for the ADC, this signal is divided by a factor of 16 using the dual D-type flip-flops (U7 and U8) and shared with the SN6505B-Q1 CLK input. The SN6505B-Q1 internally divides this clock input by another factor of 2, resulting in a transformer switching frequency that is synchronous with the ADC clock. Any remaining switching noise at the transformer output detected by the ADS131B26-Q1 aligns with a null in the ADC sinc3 digital filter response and be significantly attenuated. Figure 4-1 shows the DC/DC converter and transformer driver circuits.