SBAU413A october   2022  – may 2023

 

  1.   Abstract
  2.   Trademarks
  3. 1EVM Overview
    1. 1.1 ADS131B26Q1EVM-PDK Features
    2. 1.2 ADS131B26Q1EVM-PDK Quick-Start Guide
  4. 2Analog Interface
    1. 2.1 Terminal Blocks and Test Points
    2. 2.2 ADC1A and ADC1B
    3. 2.3 ADC2A and ADC2B
    4. 2.4 ADC3A and ADC3B
  5. 3Digital Interface
    1. 3.1 Connection to the PHI Controller
    2. 3.2 Digital Header
    3. 3.3 Clock Options
  6. 4Power Supplies
    1. 4.1 DC/DC Converter Circuit
    2. 4.2 ADC Power Supplies
    3. 4.3 Power Supply and Voltage Reference Decoupling
  7. 5ADS131B26Q1EVM-PDK Initial Setup
    1. 5.1 Default Jumper Settings
    2. 5.2 EVM Graphical User Interface (GUI) Software Installation
  8. 6ADS131B26Q1EVM-PDK Software Reference
    1. 6.1 Global Settings for ADC Control
    2. 6.2 Register Map Configuration
      1. 6.2.1 Register Map Basics
      2. 6.2.2 ADC1A, ADC3A and ADC1B, ADC3B Configuration
      3. 6.2.3 ADC2A and ADC2B Configuration
    3. 6.3 Analysis Tools
      1. 6.3.1 Time Domain Display
      2. 6.3.2 Spectral Analysis Tool
      3. 6.3.3 Histogram Analysis
      4. 6.3.4 Sequencer Analysis
  9. 7ADS131B26Q1EVM-PDK Bill of Materials, PCB Layout, and Schematics
    1. 7.1 Bill of Materials (BOM)
    2. 7.2 PCB Layout
    3. 7.3 Schematics
  10. 8Revision History

3.3 Clock Options

The ADS131B26-Q1 uses an internal oscillator by default after power-up. The internal oscillator frequency (fCLK) has a nominal frequency of 8.192 MHz and serves as the primary timing reference for both analog and digital circuitry inside the device. The ADC modulator frequency (fMOD) is equal to one-half the clock frequency (fMOD = fCLK / 2) and controls the timing of the input sample-and-hold switches inside each delta-sigma ADC modulator.

In addition to the internal oscillator, the EVM allows the user to provide an external clock to the ADS131B26-Q1 CLK pin. The user must also uninstall R71 and set DEVICE_CFG (4Ch) bit 12 = 1b when enabling the external clock source. The external clock signal can come from either:

  1. The onboard crystal oscillator (Y1), which has a nominal frequency of 8.192 MHz.
  2. An external clock source connected to the SMA connector (J10).
One advantage to using either external ADC clock option on the EVM is the ability to synchronize the DC/DC converter switching frequency with a null in the ADC digital sinc3 filter. For more information, see Section 4.1. Figure 3-1 shows a schematic of the external clock options.

GUID-20220921-SS0I-ZWXM-MNQX-PKBDFCJHZFCS-low.svgFigure 3-1 External ADC Clock Options (Schematic)