SBAU435 February   2024 ADS127L18

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1  EVM Analog Input Options
    2. 2.2  Power Requirements
    3. 2.3  ADC Connections and Decoupling
    4. 2.4  ADC Input Amplifiers
    5. 2.5  VCOM Buffer
    6. 2.6  Voltage Reference
    7. 2.7  Reference Buffer
    8. 2.8  Clock Tree
    9. 2.9  Serial Interface
    10. 2.10 EEPROM
    11. 2.11 Power Supplies
    12. 2.12 Low Dropout Regulator (LDO)
  9. 3Software
    1. 3.1 Software Description
    2. 3.2 ADS127L18 EVM Software Installation
  10. 4Implementation Results
    1. 4.1 EVM Operation
      1. 4.1.1 Evaluation Setup
      2. 4.1.2 Optional EVM Connections
      3. 4.1.3 EVM Register Settings
      4. 4.1.4 ADC Capture Settings
        1. 4.1.4.1 ADC Configuration
        2. 4.1.4.2 Clocking Configuration
        3. 4.1.4.3 SPI and Data Port Configuration
        4. 4.1.4.4 Filter Configuration
        5. 4.1.4.5 Channel Configuration
      5. 4.1.5 Time Domain Display
      6. 4.1.6 Spectral Analysis Display
      7. 4.1.7 Histogram Analysis Display
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content

Features

  • Simultaneously measure eight channels
  • Data rate up to 512 kSPS (wideband filter)
  • Data rate up to 1.365 MSPS (low-latency filter)
  • AC performance with DC precision:
    • 111.5dB dynamic range at 256 kSPS
    • -120dB THD
    • 0.9ppm of Full Scale INL
    • 50nV/°C offset drift
    • 0.6ppm/°C gain drift
  • Power-scalable speeds from 512 kSPS (28 mW/ch) to 50 kSPS (3.3 mW/ch)