SBAU435
February 2024
ADS127L18
1
Description
Get Started
Features
Applications
6
1
Evaluation Module Overview
1.1
Introduction
1.2
Kit Contents
1.3
Specification
1.4
Device Information
2
Hardware
2.1
EVM Analog Input Options
2.2
Power Requirements
2.3
ADC Connections and Decoupling
2.4
ADC Input Amplifiers
2.5
VCOM Buffer
2.6
Voltage Reference
2.7
Reference Buffer
2.8
Clock Tree
2.9
Serial Interface
2.10
EEPROM
2.11
Power Supplies
2.12
Low Dropout Regulator (LDO)
3
Software
3.1
Software Description
3.2
ADS127L18 EVM Software Installation
4
Implementation Results
4.1
EVM Operation
4.1.1
Evaluation Setup
4.1.2
Optional EVM Connections
4.1.3
EVM Register Settings
4.1.4
ADC Capture Settings
4.1.4.1
ADC Configuration
4.1.4.2
Clocking Configuration
4.1.4.3
SPI and Data Port Configuration
4.1.4.4
Filter Configuration
4.1.4.5
Channel Configuration
4.1.5
Time Domain Display
4.1.6
Spectral Analysis Display
4.1.7
Histogram Analysis Display
5
Hardware Design Files
5.1
Schematics
5.2
PCB Layouts
5.3
Bill of Materials (BOM)
6
Additional Information
6.1
Trademarks
7
Related Documentation
7.1
Supplemental Content
Features
Simultaneously measure eight channels
Data rate up to 512 kSPS (wideband filter)
Data rate up to 1.365 MSPS (low-latency filter)
AC performance with DC precision:
111.5dB dynamic range at 256 kSPS
-120dB THD
0.9ppm of Full Scale INL
50nV/°C offset drift
0.6ppm/°C gain drift
Power-scalable speeds from 512 kSPS (28 mW/ch) to 50 kSPS (3.3 mW/ch)