SBAU435 February 2024 ADS127L18
Figure 3-8 shows the different clock options for the ADS127L18EVM that are selected by jumper JP1. The default setting for JP1 is the 2-3 position (EVM CLK), which enables the local 32.768MHz oscillator (Y1) on the ADS127L18EVM board. This clock is routed to the clock input of the ADS127L18 to support all speed modes. Moving JP1 to the 1-2 position (EXT CLK) allows an external clock supplied on the SMA connector (J2). Use a CMOS square-wave signal with an amplitude equal to 1.8V (IOVDD) and a frequency within the specified range of the ADS127L18.