SBAU435 February   2024 ADS127L18

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1  EVM Analog Input Options
    2. 2.2  Power Requirements
    3. 2.3  ADC Connections and Decoupling
    4. 2.4  ADC Input Amplifiers
    5. 2.5  VCOM Buffer
    6. 2.6  Voltage Reference
    7. 2.7  Reference Buffer
    8. 2.8  Clock Tree
    9. 2.9  Serial Interface
    10. 2.10 EEPROM
    11. 2.11 Power Supplies
    12. 2.12 Low Dropout Regulator (LDO)
  9. 3Software
    1. 3.1 Software Description
    2. 3.2 ADS127L18 EVM Software Installation
  10. 4Implementation Results
    1. 4.1 EVM Operation
      1. 4.1.1 Evaluation Setup
      2. 4.1.2 Optional EVM Connections
      3. 4.1.3 EVM Register Settings
      4. 4.1.4 ADC Capture Settings
        1. 4.1.4.1 ADC Configuration
        2. 4.1.4.2 Clocking Configuration
        3. 4.1.4.3 SPI and Data Port Configuration
        4. 4.1.4.4 Filter Configuration
        5. 4.1.4.5 Channel Configuration
      5. 4.1.5 Time Domain Display
      6. 4.1.6 Spectral Analysis Display
      7. 4.1.7 Histogram Analysis Display
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content

5.2 PCB Layouts

GUID-20231215-SS0I-HLDP-L4GW-DBTN47JD559R-low.svg Figure 5-8 PCB Layout for the ADS127L18EVM (Top View)
GUID-20231215-SS0I-C7P4-Z7XG-ZSNWGL80F0MD-low.svg Figure 5-9 PCB Layout for the ADS127L18EVM (Bottom View)
GUID-20231215-SS0I-DT71-8JDV-HKWNCHDZTMPB-low.svg Figure 5-10 PCB Layout (internal AVSS/GND plane 1) for the ADS127L18EVM
GUID-20231215-SS0I-SLXZ-N894-K0XWMVR0L1KT-low.svg Figure 5-11 PCB Layout (internal AVSS/GND plane 2) for the ADS127L18EVM