SBAU435 February   2024 ADS127L18

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1  EVM Analog Input Options
    2. 2.2  Power Requirements
    3. 2.3  ADC Connections and Decoupling
    4. 2.4  ADC Input Amplifiers
    5. 2.5  VCOM Buffer
    6. 2.6  Voltage Reference
    7. 2.7  Reference Buffer
    8. 2.8  Clock Tree
    9. 2.9  Serial Interface
    10. 2.10 EEPROM
    11. 2.11 Power Supplies
    12. 2.12 Low Dropout Regulator (LDO)
  9. 3Software
    1. 3.1 Software Description
    2. 3.2 ADS127L18 EVM Software Installation
  10. 4Implementation Results
    1. 4.1 EVM Operation
      1. 4.1.1 Evaluation Setup
      2. 4.1.2 Optional EVM Connections
      3. 4.1.3 EVM Register Settings
      4. 4.1.4 ADC Capture Settings
        1. 4.1.4.1 ADC Configuration
        2. 4.1.4.2 Clocking Configuration
        3. 4.1.4.3 SPI and Data Port Configuration
        4. 4.1.4.4 Filter Configuration
        5. 4.1.4.5 Channel Configuration
      5. 4.1.5 Time Domain Display
      6. 4.1.6 Spectral Analysis Display
      7. 4.1.7 Histogram Analysis Display
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content

2.12 Low Dropout Regulator (LDO)

Figure 3-12 shows how the ADS127L18 AVDD, AVSS, and IOVDD supplies are generated. Power is provided by an external supply on either J7 or J6; refer to Section 2.11 and Figure 3-11 for more details. AVDD and IOVDD are regulated to 5V and 1.8V, respectively, using low-noise TPS7A47 LDOs. The 5V LDO output is used for the AVDD connections and can be reprogrammed to different output voltages using R44, R45, R46, R47, R48, R49 and R50. The 1.8V LDO is used for IOVDD and can be reprogrammed from 1.7V to 1.9V only.

An additional LDO generates –2.5V for AVSS using the low-noise TPS7A30 LDO. This LDO is only supplied by external power on J7. By default, AVSS is connected to GND with a shunt on jumper JP2, position 1-2. If AVSS is set to –2.5V for bipolar operation, connect an external negative supply to J7 and move the shunt on jumper JP2 to position 2-3. In this configuration, the voltage level for AVDD does not need to be changed. The 5V LDO is referenced to AVSS, so setting AVSS = -2.5V also changes the AVDD supply to 2.5V (with respect to GND).

GUID-20240108-SS0I-TTRG-JC41-SXW3QDTRLQBB-low.svgFigure 2-12 LDO Regulators 5V, 1.8V, -2.5V