The ADS9227EVM offers the following options for providing the conversion clock to the ADS9227: a CMOS clock from the TSWDC155EVM, a CMOS clock from an external source, and an LVDS clock from external source. Table 3-2 and Figure 3-7 provide an overview of the ADS9227 sample clock options available on the EVM. By default, the FPGA controller on the TSWDC155EVM (sold separately) sources a single-ended CMOS clock that can be connected directly to the SMPL_CLKP pin on the ADS9227 by configuring JP6 in the [2-3] position. Connect SMPL_CLKM to GND by installing a shunt on JP7. Lastly, install a jumper on JP5 in the [2-3] position to provide a SMPL_SYNC input from the FPGA controller, which is used to synchronize the internal averaging filter on the ADS9227 at the start of data capture. This default configuration allows the user to select the clock frequency from the options listed in the EVM GUI.

When using an external CMOS clock, move JP6 into the [1-2] position, install a shunt on JP4, and connect the external clock source to the SMA connect, J6. To use an LVDS clock, remove the jumper from JP4 and install a 100Ω resistor on the footprint for R26. Make sure that any external clock source has low jitter to maximize the performance of the ADS9227.

Figure 2-7 Sample Clock Selection