SBAU460 April   2024 PCM1841-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Overview
    2. 2.2 Hardware Configuration
      1. 2.2.1 PCM1841Q1EVM Inputs
        1. 2.2.1.1 Line Inputs
        2. 2.2.1.2 Onboard Microphone Input
    3. 2.3 Power Supply
  9. 3Hardware Design Files
    1. 3.1 PCM1841Q1EVM Schematic
    2. 3.2 PCB Layouts
    3. 3.3 PCM1841Q1EVM Bill of Materials
  10. 4Additional Information
    1. 4.1 Trademarks
  11. 5Related Documentation

2.2 Hardware Configuration

The format of the audio data and the operating mode of the ADC are controlled by the following pins: MD0, MD1, MSZ, FMT0, and FMT1. These signals are referenced to IOVDD and can be set to high (1) or low (0). If no shunt is installed, then a 10kΩ pulldown resistor sets the pin low so that the ADC remains in a defined state. Table 3-1 shows the header numbers and the pin functions and Table 3-2 shows the possible modes and output formats. The MSZ pin selects whether the device is a controller or a target on the audio bus. When MSZ is pulled high, the device is in target mode and MD1 becomes an input for MCLK. A shunt connecting J19 to the center pin of J18 routes the MCLK signal provided on J8 to the MD1 pin on the ADC to allow for easy interfacing with audio measurement equipment while in controller mode.

Table 2-1 PCM1841-Q1 EVM Headers and Jumpers
Designator Function
J1 Differential line, microphone input 1
J2 Differential line, microphone input 2
J3 Differential line, microphone input 3
J4 Differential line, microphone input 4
J5 IOVDD-SYS voltage selection (1.8V or 3.3V)
J6 +5-V supply input
J7 Connector to AC-MB
J8 Digital audio serial interface
J9 Connect AVDD to onboard 3.3V regulator
J10 Connect IOVDD to IOVDD-SYS
J13 MSZ select
J14 Connect MICBIAS to onboard microphone
J15 Microphone OUT+ to ADC IN1P
J16 Microphone OUT– to ADC IN1M
J17 MDO select
J18 MD1 select
J19 Connect MCLK to MD1
J20 FMT0 select
J21 FMT1 select
Table 2-2 PCM1841-Q1 Hardware Controllable Settings
MD0 Modes
MD0 MSZ (0 = target, 1 = controller) MDO Functional Mode
0 0 Linear phase filter
0 1 MCLK = 256 × Fs
1 0 Low latency filter
1 1 MCLK = 512 × Fs
MD1 Modes
MD1 MSZ (0 = target, 1 = controller) MD1 Functional Mode
0 0 DRE disabled
0 1 MCLK input
1 0 DRE enabled
1 1 MCLK input
Audio Output Data Format
FMT0 FMT1 Data Format
0 0 4 channel TDM
0 1 2 channel TDM
1 0 2 channel left-justified
1 1 2 channel I2S

All hardware pins are tied low by default, placing the device in target mode with a linear phase filter, DRE disabled, and 4-channel TDM audio output.

For more information on the operating modes of the PCM1841-Q1 device, see the PCM1840 Quad Channel, 32-Bit, 192kHz, Burr-Brown Audio ADC Data Sheet.