Input | Output | Supply | ||||
---|---|---|---|---|---|---|
ViMin | ViMax | VoMin | VoMax | Vcc | Vee | Vref |
–10V | 10V | –10V | 10V | 15V | –15V | 0V |
This circuit controls the slew rate of an analog gain stage. This circuit is intended for symmetrical slew rate applications. The desired slew rate must be slower than that of the op amp chosen to implement the slew rate limiter.
Transient Simulation Results
Texas Instruments, Simulation for Slew Rate Limiter, circuit SPICE simulation file
Texas Instruments, Single Op-Amp Slew Rate Limiter, reference design
OPA192 | |
---|---|
Vcc | 4.5V to 36V |
VinCM | Rail-to-rail |
Vout | Rail-to-rail |
Vos | 5µV |
Iq | 1mA/Ch |
Ib | 5pA |
UGBW | 10MHz |
SR | 20V/µs |
#Channels | 1, 2, and 4 |
OPA192 |
TLV2372 | |
---|---|
Vcc | 2.7V to 16V |
VinCM | Rail-to-rail |
Vout | Rail-to-rail |
Vos | 2mV |
Iq | 750µA/Ch |
Ib | 1pA |
UGBW | 3MHz |
SR | 2.1V/µs |
#Channels | 1, 2, and 4 |
TLV2372 |
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Changes from Revision A* (February 2019) to Revision B (October 2024)
Changes from Revision * (February 2018) to Revision A (February 2019)