Current Sense Amplifier Considerations for Driving SAR ADCs

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1 Introduction

In many modern applications, the focus in signal chain often begins with the analog to digital converter (ADC) and its specifications. The designer begins by defining the resolution needs of the their specifications and works backwards to select a suitable driver that will provide the specifications necessary to deliver the desired throughput, resolution, and noise specifications required by the system.

When working with sensors, however, the opposite is quite often the case: the designer has chosen a specific sensor, such as a current sensing amplifier (CSA), to meet a specific requirement in their respective system, and therefore the desire is to find a way to capture the maximum throughput starting from the input side of the signal chain and moving forward. This application report aims to perform this type of analysis, examining the INA293 as the chosen sensor of interest, and discussing techniques to maximize throughput. Output impedance is examined to discern when a device may be capable of driving an ADC on its own, and when a buffer would be required to ensure optimal performance.

2 The SAR ADC Switching Model

When digitizing an analog signal via an ADC, the typical goal is to drive the signal to within 1/2 an LSB inside a specified period of acquisition time. This is due to the fact that the best case error that can be achieved in an ADC is limited to this value, due to the phenomenon commonly called quantization noise.

When choosing an input driver for the front end of an ADC, to meet this goal, typically three major criterion from the ADC govern the beginning focus area of analysis: acquisition time, ADC resolution, and desired sampling rate. These factors all contribute to the needs of the driver to properly drive the inputs.

2.1 Acquisition Time

When examining the sampling scheme for a SAR ADC, it is broken down into two specific time frames: acquisition time, and conversion time. The relative flow of the capture of a single sample is shown in Typical ADC Single Acquisition Cycle , and the input structure of the ADS8860 is shown in ADS8860 Input Sampling Stage Equivalent Circuit, Hold Mode below.

Figure 2-1 Typical ADC Single Acquisition Cycle

Figure 2-2 ADS8860 Input Sampling Stage Equivalent Circuit, Hold Mode

At the beginning of the acquisition phase, the switches of the sample and hold input structure close allowing the sample and hold capacitor, C_SH, to charge. This capacitor will continue to charge until it either settles to a final value, or the end of the acquisition period is reached, at which point the switch re-opens and conversion begins. The goal of a successful design is to ensure that this sample is sufficiently charged within the acquisition window of the ADC, to prevent any additional error greater than the quantization noise of the ADC on the measurement.

Immediately following the acquisition time, the ADC begins operation on the sampled value and digitizes the information. The time in which this occurs is called the conversion time. This is the time required by the ADC to convert the measured result into a digital value. Once this value is completed, it is delivered to the host processor, and the next sample and hold cycle begins.

The conversion time for any ADC is typically a fixed value inherent to the device, and remains fixed regardless of the value of the sampling clock.