6 Input Bias Current versus Bias Transients

Up to this point, this article focused on bias current transients due to charge injection and clock feedthrough in the input MOSFET switches. Beyond this effect, there is a DC bias current on all CMOS amplifiers due to the leakage of ESD diodes. This ESD leakage varies somewhat for different op-amp models, but typically the leakage is in the low picoamps range at room temperature. The bias current specified for chopper amplifiers is the average of the transient current from chopper-switch charge injection combined with the ESD diode leakage. Compared to the magnitude of the current transients these bias currents are generally negligible at room temperature, but can become significant at higher temperatures. For example, for OPA186 the typical bias current increases from ±5pA at 25°C, to ±900pA at 125°C (see Figure 6-1). This increase in bias current is mainly due to the change in ESD diode leakage because the MOSFET switch charge injection remains relatively constant over temperature.

Therefore, in addition to using Table 5-1 to select a source impedance that does not generate significant offset due to the bias transients, it is important to make sure that increasing bias current over temperature does not translate into significant input offset voltage. Equation 3 can be used to calculate I_B over temperature given the maximum value at 125°C from the data sheet table. This equation is based on the principle that the ESD diode leakage increases roughly double for every 10°C increase in temperature. Equation 4 uses the bias current at temperature and the offset voltage to determine the maximum resistance to be used due to bias current. Example 1 applies the equations to the OPA186 at 100°C. Based on this example, the OPA186 can be used up to 100°C with 11.7kΩ source impedance or feedback impedance with minimal impact on offset. Note that Table 5-1 recommends using resistances less than 500kΩ. This recommendation is correct for room temperature, but at 100°C lower impedances are required because bias current increases at high temperature. Thus, for higher temperature applications, it is necessary to look at both Table 5-1 and also the data sheet bias current specification over temperature to determine the maximum source and feedback impedances.

where

I_B(T) – I_B and any temperature greater than 25°C

I_B(125C) – maximum I_B specified at 125°C

T – Temperature in degrees °C

where

R_MAX – the maximum recommended resistance that avoids translation of bias current into offset

I_B(T) – I_B calculation from Equation 3

V_osMax – Maximum input offset specified in op amp data sheet

Example 1: OPA186 at 100°C

Bias current cancellation is a method where the input impedance and feedback network impedance are balanced to make the inverting and noninverting bias current offset equal so that they cancel. However, this method only works when the bias currents are approximately equal. The bias current offset (I_BOS) specification is a measurement of how close the bias current are to each other (I_BOS = I_BP – I_BN). For bias current cancellation to be effective the bias current offset must be much less than bias current (I_BOS << I_B). Bias current cancellation can help to minimize the effect of bias current transients if the transient amplitude and wave shape is well balanced between the inverting and non-inverting inputs. Unfortunately, there is generally some imbalance in the bias current transient amplitude. Furthermore, parasitic capacitances and filter capacitances influence the bias current transients. To avoid translation of bias current transients into offset voltage, keeping the source and feedback resistance below the minimum specified in Table 5-1 is recommended, rather than relying upon bias current cancellation to minimize offset. Considering DC bias currents, balancing source and feedback impedance can be helpful at higher temperatures as bias current offset (I_BOS) is often significantly lower than bias current at high temperatures.