SBOA589 Application brief

SBOA589 May 2024 INA849 , JFE2140

Introduction

Sensors with a high source impedance can be purely resistive, capacitive, inductive or a combination of the three. High source impedance sensors that produce small signals on the order of a few thousandths of a volt often require amplfication from a low noise and high input impedance pre-amplifier. Amplifiers with bipolar junction transistor (BJT) input stages are popular for the low voltage noise characteristics. BJT devices typically have higher current noise compared to the complementary metal-oxide semiconductor (CMOS)-input and junction field-effect transistor (JFET)-input counterparts. When paired with high source impedance sensors, the current noise from BJT input stages translates into an increase of additional voltage noise. Using a complementary metal-oxide semiconductor (CMOS) device is a good choice for a high input impedance; however, the noise performance is worse than that of a bipolar input. The discrete junction field-effect transistor (JFET) has better 1/f noise performance than the CMOS device and also has high input impedance. More details are found in the Trade-offs Between CMOS, JFET, and Bipolar Input Stage Technology application report. This application brief discusses how to interface high source impedance sensors with high current noise BJT instrumentation amplifiers using discrete matched JFETs. Two preamplifier topologies are compared in this application brief with analysis of trade-offs and how to decide when to use one topology over the other.

Preamplifer Topologies

Figure 1 shows a preamplifier topology using the INA849. The INA849 is biased with a single supply of 12V. The OPA145 outputs a mid-supply DC voltage of 6V and drives the reference pin R_ef and the input common mode voltage of the INA849. The INA849 has a BJT input stage with ultra low voltage noise. BJT input stages are popular choices for the low voltage noise characteristics. When paired with high source impedance sensors the current noise from BJT input stages translates into an additional voltage noise.

Figure 1 INA Preamplifier

A discrete JFET such as TI's JFE2140, when followed by a bipolar instrumentation amplifier such as the INA849, offers a way to achieve high input impedance and low noise with flexible biasing, see Figure 2. The JFETs Q_1A and Q_1B are each configured in a source follower configuration and replace the front end of the INA849. The INA849 is configured in a gain of 60dB. Source impedances R_source1 and R_source2 are now connected to the high input impedance and low current noise discrete JFET front end. The discrete JFET and INA preamplifier circuit offers the low input current noise of the JFETs and the low voltage noise of the INA.

JFE2140 INA849 Discrete JFET and INA
Preamplifier

Figure 2 Discrete JFET and INA Preamplifier

Noise

Figure 3 shows noise performance comparisons between the two preamplifier topologies shown in Figure 1 and Figure 2 with various source impedances R_source. With low source impedance sensors the INA849 outperforms the JFET design. As R_source increases the preamplifier shown in Figure 2 outperforms the INA849 alone.

Figure 3 Preamplifier Noise Comparison with Various Source Impedances

Table 1 shows the total circuit current consumption and noise tradeoffs between the two preamplifier topologies. The total current consumption from the design shown in Figure 1 is 6.71mA. The total current consumption of the JFET front end design shown in Figure 2 is 9.88mA. This represents a 47.2% increase in total current consumption. The addition of the discrete JFETs improves the noise performance by reducing the input referred broadband noise by -64.4% when using a source impedance of R_source = 100kΩ. Figure 3 shows the improvement in the $\frac{1}{f}$ noise when using the JFET + INA849 topology paired with high source impedances.

Table 1 Preamplifier Topology Comparison

Preamplifier Topology	Total Iq (mA)	Percent Increase in Iq	Total Voltage Noise $(\frac{n V}{\sqrt{H z}})$ Input Referred f = 1kHz	Percent Decrease in Voltage Noise R_source = 100kΩ
INA849	6.71	-	162.07	-
JFET + INA849	9.88	47.2%	57.63	-64.4%

When deciding to use one of the two topologies shown in Figure 1 and Figure 2 a simple calculation is used. In general if $R_{s o u r c e} > \frac{4 k T}{{(i_{n})}^{2}}$ the use of the JFET input devices results in lower noise. Additional detail can be found in the application note Impact of Current Noise in CMOS and JFET Amplifiers. The INA849 has a typical current noise specification of $i_{n} = 1.1 \frac{p A}{\sqrt{H z}}$ .

Equation 1.

R_{s o u r c e} > \frac{4 \times 1.38 \times 10^{- 23} \times (273.15 ˚ + 25)}{{(1.1 \times 10^{- 12})}^{2}}

Equation 2.

R_{s o u r c e} > 13.6 k Ω

When R_source = 13.6kΩ, Table 2 shows that e_nR = e_{ni_INA} = 21.16 (nV/√Hz). Following this guidance there is a $\sqrt{2}$ improvement in noise when using the discrete JFET and INA preamplifier from Figure 2.

Table 2 Source Impedance and Calculated Noise Comparison

R_source(Ω)	e_nR (nV/√Hz)	e_{ni_INA}(nV/√Hz)	INA Calculated Total Input Referred Noise e_{n_Total_INA}(nV/√Hz)	JFET + INA Calculated Total Input Referred Noise e_{n_Total_JFET_INA}(nV/√Hz)
100	1.81	0.16	2.08	2.56
500	4.06	0.78	4.25	4.44
1000	5.74	1.56	6.03	6.01
1,360	6.69	2.12	7.09	6.93
5,000	12.83	7.78	15.04	12.95
10,000	18.14	15.56	23.92	18.23
13,600	21.16	21.16	29.94	21.23
50,000	40.57	77.78	87.73	40.61

The values in Table 2 are calculated using Equation 3 through Equation 6 where the values shown in Table 3 are used.

Table 3 Table of Values

Value	Description
$k_{B} = 1.38 \times 10^{- 23} J K^{- 1}$	Boltzmann Constant
$T = 298.15 K$	Temperature in Kelvin
$e_{n_J F E T} = 1.5 \frac{n V}{\sqrt{H z}}$	Broadband Voltage Noise of JFE2140 Biased at 1.59mA, f = 1kHz
$e_{n_I N A} = 1 \frac{n V}{\sqrt{H z}}$	Broadband Voltage Noise of INA849 G = 60dB, f = 1kHz
$i_{n} = 1.1 \frac{p A}{\sqrt{H z}}$	Broadband Current Noise of INA849 G = 60dB, f = 1kHz

The preamplifier topologies have balanced inputs. For this reason a $\sqrt{2}$ factor is used in Equation 3 and Equation 4.

Equation 3.

e_{n R} = \sqrt{2} \sqrt{4 k_{B} T R_{S o u r c e}}

Equation 4.

e_{n i_I N A} = \sqrt{2} R_{S o u r c e} i_{n}

Equation 5.

e_{n_T o t a l_I N A} = \sqrt{{e_{n R}}^{2} + {e_{n i_I N A}}^{2} + {e_{n_I N A}}^{2}}

Equation 6.

e_{n_T o t a l_J F E T_I N A} = \sqrt{{e_{n R}}^{2} + {e_{n_I N A}}^{2} + {e_{n_J F E T}}^{2}}

Design Considerations

Discrete JFETs offer bias flexibility by adjusting the drain to source voltage V_DS and gate to source voltage V_GS. A few key JFET biasing considerations can be made when designing the preamplifier topology shown in Figure 2. Figure 4 shows the drain to source current I_DS vs V_DS. Bias the JFETs with sufficient V_DS to operate in the saturation region.

Figure 4 I_D vs V_DS

Figure 5 shows I_G vs V_DS. Bias V_DS such that the gate current is lower than the INA849 bias current.

Figure 5 I_G vs V_DS