SBOA590 November   2024 OPA186 , OPA206 , OPA328 , OPA391 , OPA928

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Input Offset Voltage (VOS) Definition
    1. 1.1 Input Offset Voltage Drift (dVOS/dT) Definition
    2. 1.2 VOS and VOS Temperature Drift Inside the Amplifier
    3. 1.3 Laser Trim to Adjust Performance
    4. 1.4 Package Trim (e-Trim™) to Adjust Performance
  5. 2Input bias current (IB) definition
    1. 2.1 Input Bias Current (IB) and IB Temperature Drift Inside the Amplifier
    2. 2.2 Derivation of IB Conversion to VOS
    3. 2.3 Internal Bias Current Cancelation
    4. 2.4 Super Beta Input Transistors
  6. 3Other Factors Influencing Offset
    1. 3.1 Finite Open Loop Gain (AOL)
    2. 3.2 Common Mode Rejection Ratio (CMRR)
    3. 3.3 Power Supply Rejection Ratio (PSRR)
    4. 3.4 AOL, CMRR, and PSRR Over Frequency
    5. 3.5 Electromagnetic Interference Ratio (EMIRR)
    6. 3.6 Mechanical Stress Induced Offset Shift
    7. 3.7 Parasitic Thermocouples
    8. 3.8 Flux Residue and Cleanliness
  7. 4Zero-drift Amplifiers to Minimize VOS and VOS Drift
  8. 5Calibration of VOS, IB, and Gain Error
  9. 6References
  10. 7Revision History

1.1 Input Offset Voltage Drift (dVOS/dT) Definition

The input offset voltage is specified at room temperature (25°C), and across temperature (VOS drift, or dVOS/dT). For precision devices, typical VOS drift maximum specifications range from 0.001 µV/°C to 5 µV/°C. Cost optimized and high-speed devices are generally not optimized for input offset voltage and VOS temperature drift, so they can have drifts as high as 100 µV/°C (see Table 1-1). The change in offset due to VOS drift can be estimated by multiplying the change in temperature relative to 25°C by the VOS drift term, ΔVOS = (dVos/dT)(T - 25°C). The change in offset due to temperature drift adds to the initial room temperature VOS. This calculation assumes that the amplifier VOS drift is linear over temperature which may not be true for all amplifiers. Some amplifier data sheets provide a graph of VOS versus temperature, which is useful to understand the linearity of the drift. Figure 1-4 shows this calculation at a temperature of 125°C for OPA2205 using the maximum specified offset and drift. In this example, the room temperature VOS is 15 μV and the VOS drift is 20 μV for a total VOS of 35 μV at 125°C.

OPA206 Maximum Input Offset Voltage Drift Model And Calculation for OPA2205 Figure 1-4 Maximum Input Offset Voltage Drift Model And Calculation for OPA2205
Equation 9. T   =   125 ℃
Equation 10. G = R F R G + 1 = 99 k Ω 1 k Ω + 1 = 100 V / V
Equation 11. V O S T = V O S 25 ℃ - d V O S d T T   -   25 ℃
Equation 12.   V O S 125 ℃ = 15 μ V - 0.2 μ V / ℃ 125 ℃   -   25 ℃   =   35 μ V
Equation 13. V O U T = V O S G = 35 μ V ( 100 V / V ) = 3.5 m V
Table 1-1 Range of VOS and VOS Drift for Different Amplifier Types
Op Amp VOS (max) (high grade) VOS Drift (max)(high grade) Technology

OPA387

2µV

0.012µV/°C

Low voltage Zero-Drift CMOS

OPA182

4µV

0.012µV/°C

High Voltage Zero-Drift CMOS

OPA2186

10µV

0.04µV/°C

24V Zero-Drift CMOS

OPA192

25µV

0.5µV/°C

e-Trim™ High Voltage CMOS

OPA210

35µV

0.5µV/°C

Super-Beta Bipolar

OPA827

150 µV

1.5 µV/°C

JFET input, Laser Trim, Bipolar

OPA828

300µV

1.3µV/°C

DiFET (JFET), Laser trimmed

LMV841

500µV

5µV/°C

12V CMOS

OPA835

1.85mV

13.5µV/°C

High Speed Bipolar

LM741

3mV

15µV/°C

Bipolar commodity (lower cost)