SBOA590 November   2024 OPA186 , OPA206 , OPA328 , OPA391 , OPA928

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Input Offset Voltage (VOS) Definition
    1. 1.1 Input Offset Voltage Drift (dVOS/dT) Definition
    2. 1.2 VOS and VOS Temperature Drift Inside the Amplifier
    3. 1.3 Laser Trim to Adjust Performance
    4. 1.4 Package Trim (e-Trim™) to Adjust Performance
  5. 2Input bias current (IB) definition
    1. 2.1 Input Bias Current (IB) and IB Temperature Drift Inside the Amplifier
    2. 2.2 Derivation of IB Conversion to VOS
    3. 2.3 Internal Bias Current Cancelation
    4. 2.4 Super Beta Input Transistors
  6. 3Other Factors Influencing Offset
    1. 3.1 Finite Open Loop Gain (AOL)
    2. 3.2 Common Mode Rejection Ratio (CMRR)
    3. 3.3 Power Supply Rejection Ratio (PSRR)
    4. 3.4 AOL, CMRR, and PSRR Over Frequency
    5. 3.5 Electromagnetic Interference Ratio (EMIRR)
    6. 3.6 Mechanical Stress Induced Offset Shift
    7. 3.7 Parasitic Thermocouples
    8. 3.8 Flux Residue and Cleanliness
  7. 4Zero-drift Amplifiers to Minimize VOS and VOS Drift
  8. 5Calibration of VOS, IB, and Gain Error
  9. 6References
  10. 7Revision History

Laser Trim to Adjust Performance

Both laser trimming and package trimming are methods for adjusting the value of resistors on the die for op amp and other semiconductor devices. Laser trimming adjusts the resistors by cutting away material on the resistors using a laser beam. Normally laser trimming is used on thin film resistors. Figure 1-9 shows a picture of an op amp die that uses laser trimming to adjust VOS, and quiescent current (IQ). The coarse laser trim adjustment effectively makes the current path longer which significantly increases the resistance. The fine laser trim adjustment makes the resistor width narrower and consequently introduces a smaller more gradual increase in resistance.

OPA206 Coarse and Fine Laser Trim of
                    Thin Film Resistors Figure 1-9 Coarse and Fine Laser Trim of Thin Film Resistors

Laser trimming is done when the device is in wafer form before packaging. A typical op amp wafer has tens of thousands of devices on it. Each device, or die, is tested by applying the electrical signals through probes that contact the pads. During the test various parameters such as VOS are measured and the laser is used to reduce the offset by making the appropriate adjustments in the trim resistors. Figure 1-10 illustrates a simplified view of the wafer, probe card, and laser. The wafer is brought into contact with the probes by moving the wafer chuck up and down. Different die on the wafer are selected by moving the chuck right and left. Figure 1-11 shows a zoomed in view of the probes in contact with a single die.

OPA206 Laser Probe Hardware (side
                    view) Figure 1-10 Laser Probe Hardware (side view)
OPA206 Laser Probe Card in Contact
                    with Die (zoomed in, top view) Figure 1-11 Laser Probe Card in Contact with Die (zoomed in, top view)

After wafer probing is complete the wafer is sawed into individual die which would then be glued to a lead frame, its pads wire bonded to appropriate pins, and finally encapsulated in plastic (see Figure 1-12). The packaging process introduces physical stress (bending, warping) on the die that causes shifts in device performance. For example, during laser trim the offset might be trimmed to a level of 10 µV, but the packaging introduces stress that shifts the offset to 100 µV. This package shift can be somewhat mitigated by careful symmetrical layout and inter-digitation of key components, however, it is not possible to completely eliminate this error source. Thus, laser trimming has inherent accuracy limitations and is the main reason why wafer trimmed parts cannot achieve single digit microvolts offset.

OPA206 Cutaway Diagram of Die
                    Packaged in SOIC Figure 1-12 Cutaway Diagram of Die Packaged in SOIC