SBOA590 November   2024 OPA186 , OPA206 , OPA328 , OPA391 , OPA928

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Input Offset Voltage (VOS) Definition
    1. 1.1 Input Offset Voltage Drift (dVOS/dT) Definition
    2. 1.2 VOS and VOS Temperature Drift Inside the Amplifier
    3. 1.3 Laser Trim to Adjust Performance
    4. 1.4 Package Trim (e-Trim™) to Adjust Performance
  5. 2Input bias current (IB) definition
    1. 2.1 Input Bias Current (IB) and IB Temperature Drift Inside the Amplifier
    2. 2.2 Derivation of IB Conversion to VOS
    3. 2.3 Internal Bias Current Cancelation
    4. 2.4 Super Beta Input Transistors
  6. 3Other Factors Influencing Offset
    1. 3.1 Finite Open Loop Gain (AOL)
    2. 3.2 Common Mode Rejection Ratio (CMRR)
    3. 3.3 Power Supply Rejection Ratio (PSRR)
    4. 3.4 AOL, CMRR, and PSRR Over Frequency
    5. 3.5 Electromagnetic Interference Ratio (EMIRR)
    6. 3.6 Mechanical Stress Induced Offset Shift
    7. 3.7 Parasitic Thermocouples
    8. 3.8 Flux Residue and Cleanliness
  7. 4Zero-drift Amplifiers to Minimize VOS and VOS Drift
  8. 5Calibration of VOS, IB, and Gain Error
  9. 6References
  10. 7Revision History

3.3 Power Supply Rejection Ratio (PSRR)

The power supply rejection ratio (PSRR) for an op amp is defined as the change in VOS versus change in the power supply voltage of the op amp. For an ideal op amp, the power supply voltage do not affect VOS (i.e. PSRR is infinite). For a practical op amp, however, the PSRR ranges from 60 dB to 166 dB (1000 µV/V to 0.005 µV/V). The equation for PSRR is PSRR = ΔVOS/ ΔVS or 20log(ΔVOS/ ΔVS) in decibels. Figure 3-6 shows a buffer amplifier in a gain of 1V/V where the noninverting input is grounded. Both the positive and negative supply are shifted in equal amounts to maintain a 0 V common mode voltage. Because VCM = 0 V and VOUT = 0 V, the CMRR and AOL does not change the offset, so the power supply rejection is the only factor shifting offset.

The specifications for the OPA210 example are shown in Table 3-1. Based on the specification, you would expect the typical offset to be ±5 µV. Notice the test condition listed at the top of the table indicates that the parameters all assume VS =±15 V, and VCM = VOUT = midsupply. In this case, VCM and VOUT are at midsupply (VCM = VOUT =0 V), but the supply is shifted from ±15 V to ±10 V. The 10V change in VS voltage causes a corresponding 0.5µV change in offset (see calculation Equation 34, and simulation Figure 3-6).

Equation 34. ΔVOS=ΔVSPSRR(lin)=10V10146/20=0.5 μV
OPA206 VOS Shift Due to PSRR on OPA210 Difference Amp Configuration Figure 3-6 VOS Shift Due to PSRR on OPA210 Difference Amp Configuration

Making an asymmetrical change in the power supply voltage causes a shift in VOS due to both common mode rejection and power supply rejection. Remember, the test condition at the top of the specification table says that VCM = VOUT = mid-supply. For a ±15 V supply, midsupply is 0 V, so VCM = 0 V meets the test condition. When an asymmetric change is made on the power supply, the common mode voltage shifts relative to the test condition. For example, if the supply changes from (+15 V, -15 V) to (+15 V, -5 V), midsupply value shifts from 0 V to 5 V. This is effectively a 5 V change in common mode and VOUT as well as a 10 V change in power supply, so PSRR, AOL, and CMRR must be considered. Conversely, if the supply changes from (+15 V, -15V) to (+10 V, -10 V), midsupply is 0 V, for both cases, and only PSRR impacts VOS.

OPA206 VOS Shift Due to PSRR and CMRR When Supplies Are Asymmetrical Figure 3-7 VOS Shift Due to PSRR and CMRR When Supplies Are Asymmetrical