SBOA590 November   2024 OPA186 , OPA206 , OPA328 , OPA391 , OPA928

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Input Offset Voltage (VOS) Definition
    1. 1.1 Input Offset Voltage Drift (dVOS/dT) Definition
    2. 1.2 VOS and VOS Temperature Drift Inside the Amplifier
    3. 1.3 Laser Trim to Adjust Performance
    4. 1.4 Package Trim (e-Trim™) to Adjust Performance
  5. 2Input bias current (IB) definition
    1. 2.1 Input Bias Current (IB) and IB Temperature Drift Inside the Amplifier
    2. 2.2 Derivation of IB Conversion to VOS
    3. 2.3 Internal Bias Current Cancelation
    4. 2.4 Super Beta Input Transistors
  6. 3Other Factors Influencing Offset
    1. 3.1 Finite Open Loop Gain (AOL)
    2. 3.2 Common Mode Rejection Ratio (CMRR)
    3. 3.3 Power Supply Rejection Ratio (PSRR)
    4. 3.4 AOL, CMRR, and PSRR Over Frequency
    5. 3.5 Electromagnetic Interference Ratio (EMIRR)
    6. 3.6 Mechanical Stress Induced Offset Shift
    7. 3.7 Parasitic Thermocouples
    8. 3.8 Flux Residue and Cleanliness
  7. 4Zero-drift Amplifiers to Minimize VOS and VOS Drift
  8. 5Calibration of VOS, IB, and Gain Error
  9. 6References
  10. 7Revision History

1.4 Package Trim (e-Trim™) to Adjust Performance

Every amplifier at Texas Instruments undergoes a final test of the device in package form. The final test applies power and electrical signals to the device and measures performance. This measurement compares against the specifications given in the product data sheet. Devices that do not meet specifications are discarded. For devices that use package level trimming (e-Trim®), parameters such as VOS are adjusted during final test to optimize performance. This adjustment is done by measuring the offset and adjusting a resistance value to minimize the error. In package trimming the internal trim resistors are divided into binary weighted segments. These segments can be added to the resistor by opening a fusible link or by using a one-time-programable (OTP) nonvolatile memory. Modern designs at Texas Instruments are mainly done using OTP.

Figure 1-13 shows a simplified view of how the resistor value is adjusted with package trimming. During final test the initial VOS is measured, and the desired trim resistor value is calculated based on the measurement. A digital signal is applied to the device through the output pin to program the OTP memory. The OTP is used to open switches in parallel with the resistor segments. The example shows that the binary weighted resistor can have a value from 0 Ω to 15 kΩ in 1 kΩ increments. When the test procedure completes, the signal sends a write protect command the device to disable the digital interface so that in the future it is not possible to accidentally re-program the OTP. After programming, the op amp reads the OTP during the startup period and the device configures the switches to set the trim resistor to its target value.

OPA206 Package trim resistor configuration Figure 1-13 Package trim resistor configuration

Figure 1-14 shows a simplified view of how the digital signals are applied to the device. Remember, the device is packaged and op amps normally do not have any pins for a digital interface. For op amps, the output pin is initially used to apply the digital signal. The device places the output in one of three states: sourcing 5 mA, sinking 5 mA, or floating. A comparator circuit detects these output current loads and creates two digital signal patterns. The digital signals drive the state machine which is used to program the OTP.

OPA206 Package Trim Communication Figure 1-14 Package Trim Communication