SBOA594 August   2024 OPA2990

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Circuit Description
  6. 3 Supporting Multiple Output Ranges
  7. 4 Resistor Sizing, M2 Selection, and Other Design Considerations
  8. 5 Mode and Range Control
  9. 6 Supply Level for Current Output
  10. 7 Supply Levels for Voltage Output
  11. 8 Protection Features
  12. 9 Measurement Results
  13. 10Power Consumption
  14. 11Error Monte-Carlo Analysis
  15. 12Rise and Fall Times
  16. 13Building Multi-Channel Output
  17. 14Summary
  18. 15References

4 Resistor Sizing, M2 Selection, and Other Design Considerations

Resistor sizing for current path starts with R5, lower value means smaller headroom, but U2 inputs closer to supply as well which can violate input common mode. R5=49.9 Ohm is reasonable choice.

The R4:R5 ratio determines the ratio of the current in M1 to the output current in M2. Lower Intermediate current (in M1) means lower current consumption, but increases output noise and degrades dynamic performance. We select a ratio of 1:10, hence R4=499Ω.

With the maximum I(M1)=2mA determined, R3=1.24kΩ.

R12=10 kΩ is used to pull-up M2 gate, while C2=C3=200pF are used to compensate U1 and U2.

M2 choice is driven by the maximum power dissipation assume 24V×20mA which is about 0.5W, and the maximum Vce voltage expected, >40V device is required. DMP6110SVT-7 is 1.2W, 60V PMOS that can be used in this circuit. M1 selection is less critical. PMV88ENEAR 0.6W, 60V NMOS is selected.

For voltage mode, R7, R8 and R9 are chosen to minimize power consumption without increasing output noise. R8=34kOhm, R7=11.3kΩ, and R9=8.45kOhm are selected.