SBOS780C March   2016  – June 2021 THS3215

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: D2S
    6. 6.6  Electrical Characteristics: OPS
    7. 6.7  Electrical Characteristics: D2S + OPS
    8. 6.8  Electrical Characteristics: Midscale (DC) Reference Buffer
    9. 6.9  Typical Characteristics: D2S + OPS
    10. 6.10 Typical Characteristics: D2S Only
    11. 6.11 Typical Characteristics: OPS Only
    12. 6.12 Typical Characteristics: Midscale (DC) Reference Buffer
    13. 6.13 Typical Characteristics: Switching Performance
    14. 6.14 Typical Characteristics: Gain Drift
  7. 7 Parameter Measurement Information
    1. 7.1 Overview
    2. 7.2 Frequency Response Measurement
    3. 7.3 Harmonic Distortion Measurement
    4. 7.4 Noise Measurement
    5. 7.5 Output Impedance Measurement
    6. 7.6 Step-Response Measurement
    7. 7.7 Feedthrough Measurement
    8. 7.8 Midscale Buffer ROUT Versus CLOAD Measurement
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential to Single-Ended Stage (D2S) With Fixed Gain of 2 V/V (Pins 2, 3, 6, and 14)
      2. 8.3.2 Midscale (DC) Reference Buffer (Pin 1 and Pin 15)
      3. 8.3.3 Output Power Stage (OPS) (Pins 4, 7, 9, 10, 11, and 12)
        1. 8.3.3.1 Output DC Offset and Drift for the OPS
        2. 8.3.3.2 OPS Harmonic Distortion (HD) Performance
        3. 8.3.3.3 Switch Feedthrough to the OPS
        4. 8.3.3.4 Driving Capacitive Loads
      4. 8.3.4 Digital Control Lines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Full-Signal Path Mode
        1. 8.4.1.1 Internal Connection With Fixed Common-Mode Output Voltage
        2. 8.4.1.2 Internal Connection With Adjustable Common-Mode Output Voltage
        3. 8.4.1.3 External Connection
      2. 8.4.2 Dual-Output Mode
      3. 8.4.3 Differential I/O Voltage Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Applications
        1. 9.1.1.1 High-Frequency, High-Voltage, Dual-Output Line Driver for AWGs
          1. 9.1.1.1.1 Design Requirements
          2. 9.1.1.1.2 Detailed Design Procedure
          3. 9.1.1.1.3 Application Curves
        2. 9.1.1.2 High-Voltage Pulse-Generator
          1. 9.1.1.2.1 Design Requirements
          2. 9.1.1.2.2 Detailed Design Procedure
          3. 9.1.1.2.3 Application Curves
        3. 9.1.1.3 Single-Supply, AC-Coupled, Piezo Element Driver
          1. 9.1.1.3.1 Detailed Design Procedure
        4. 9.1.1.4 Output Common-Mode Control Using the Midscale Buffer as a Level Shifter
          1. 9.1.1.4.1 Detailed Design Procedure
        5. 9.1.1.5 Differential I/O Driver With independent Common-Mode Control
          1. 9.1.1.5.1 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 TINA-TI (Free Software Download)
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
9.1.1.5.1 Detailed Design Procedure

Certain applications require the differential DAC output voltage to be translated from one common-mode (compliance) level to a differential output at a different common-mode level. The THS3215 performs voltage-level translation directly using the very flexible blocks provided internally. Figure 9-11 shows an example of such an application, where the differential gain is always 4 V/V. The differential gain is fine-tuned down by setting the insertion loss in the differential post-filter. The considerations critical to this application include:

  1. The input is dc-coupled with the appropriate termination impedance required by the DAC. Use a high-frequency, antialiasing filter at the input to limit DAC feedthrough in the deselected OPS internal input.
  2. The output common-mode control is set with the voltage applied to the VMID buffer input at VMID_IN (pin 1). The circuit is configured so that the output at VMID_OUT (pin 15) drives both VREF (pin 14), in order to set the D2S dc output voltage, and VIN+ (pin 9).
  3. The D2S output available at VO1 (pin 6) provides one side of the differential-output, and is dc-biased at VMID_OUT. VO1 also drives the RG resistor for the OPS in an inverting gain of –1 V/V. The dc bias level at the RG input and the VIN+ input of the OPS are the same voltage; therefore, no level shift through the OPS occurs. The OPS outputs an inverted version of the D2S output signal at the same common-mode voltage (VMID_OUT). The wideband, differential signal with independent output common-mode voltage control can now be applied to a differential filter and on to the next stage.
  4. Make sure that the differential filter has only differential resistors and capacitors. Termination resistors to ground level-shift the input common-mode voltage, while differential resistors transfer VMID_OUT directly through the filter as a common-mode input to the mixer.
  5. If the desired VMID_OUT + differential signal combined clips in the OPS or D2S, offset the supplies to gain headroom. For instance, if a 5 V output common-mode voltage is required with a 10 VPP differential signal, the OPS and D2S must deliver 2.5 V to 7.5 V output swings. The D2S has the higher headroom requirement at 1.5 V (maximum). Operating the THS3215 with –5 V and 10 V supplies stays within the rated maximum of
    15.8 V total supply range, and provide adequate headroom for the positive offset swing requirement. Note that the logic lines are still referenced to GND by pin 7. Tie PATHSEL (pin 4) to +VCC to hold this design in the external path mode required.