The THS3215 provides two logic input lines that control the input path to the OPS and the OPS power disable feature; both are referenced to GND (pin 7). The control logic defaults to a logic-low state when the pins are externally floated. The GND pin must have a dc path to some reference voltage for correct operation. Float the two logic control lines to enable the OPS and select the internal path connecting the D2S internal output to the OPS noninverting input. Figure 8-14 shows a simplified internal schematic for either logic control input pin.

The Q2 branch of the differential pair sets up a switch threshold approximately 1 V greater than the voltage applied to the GND pin. If the control input is floating or < 0.7 V, the differential-pair tail current diverts to the
100-Ω detector load, and results in an output voltage (V_CTRL, shown in Figure 8-14) that activates the desired mode. The floated pin default voltage is the PNP base current into the 19 kΩ resistor. As the control pin voltage rises above 1.3 V, the differential-pair current is completely diverted away from the 100 Ω side, thus switching states.

This unique design allows the logic control inputs to be connected to a single-supply as high as 15.9 V, in order to hold the inputs permanently high, while still accepting a low ground-referenced logic swing for single-supply operation. The NPN transistor (Q3) and two diodes (D1 and D2) act as a clamp to prevent large voltages from appearing across the differential stage.

When the OPS is disabled, both input paths to the OPS are also opened up regardless of the state of PATHSEL (pin 4).