The very-high peak output current and slew rate of the THS3215 OPS make it particularly suitable for driving heavy capacitive loads, such as the piezo elements used in continuous wave (CW) applications that require high-amplitude, sinusoidal-type excitations. The driver is quickly disabled during the receive time when the output transmit and receive switch is moved to receive mode. Figure 9-9 shows an example design using the internal midscale buffer to bias all the stages to midsupply on a single 15 V design. There are many elements to this example that also apply to any single-supply application. The key points here are:

1. The differential DAC input signal is ac-coupled to the D2S input, and the termination resistors are scaled up and biased to midsupply using the output of the midscale buffer, VMID_OUT (pin 15). The 10-nF blocking capacitors before the 1.62 kΩ termination resistors set the high-pass pole at 10 kHz.
2. The internal divider resistors of the midscale buffer are decoupled using a 1 µF capacitor on VMID_IN (pin 1). Use of the capacitor improves both noise and PSRR through the reference buffer stage. In turn, the noise injected by the bias source is reduced at the various places the buffer output is used.
3. V_{MID_OUT} is also applied to the VREF input (pin 14) to hold the D2S output centered on the single 15 V supply. There is minimal dc current into VREF because the D2S input buffers operate at the same common-mode voltage, V_{MID_OUT}.
4. The D2S output is dc biased at midsupply and delivers two times the differential swing applied at its inputs. Assuming 2 V_PP at the D2S inputs implies 4 V_PP at the D2S output pins. Lower input swings are supported with the gain in the OPS adjusted to meet the desired output maximum.
5. The filter in Figure 9-9 is a 0.2 dB ripple, second-order Chebyshev filter at 15 MHz. For example, if the desired maximum frequency is 12 MHz, this filter attenuates the HD2 and HD3 out of the D2S by approximately 3 dB and 5 dB, respectively. Increased attenuation can be provided with higher-order filters, but this simple filter does a good job of band-limiting the high-frequency noise from the D2S outputs before the noise gets into the OPS.
6. The dc bias voltage at VO1 (pin 6) drives a small dc current into the 18.5 kΩ resistor to ground at the OPS external input, VIN+ (pin 9). The error voltage due to the bias current level-shifts the dc voltage at the OPS noninverting input through the 105 Ω filter resistor. This offset is amplified by the OPS gain because the R_G element is referenced to the V_MID output with a dc gain of 3.4 V/V.
7. The logic lines are still referenced to ground in this single-supply application. The external path to the OPS is selected by connecting PATHSEL (pin 4) to +V_CC. DISABLE (pin 10) is grounded in this example in order to hold the OPS on. If the disable feature is required by the application, drive DISABLE (pin 10) using a standard logic control driver. Note that the midscale buffer output still drives R_G and R_F to midsupply in this configuration with the OPS disabled.
8. To operate at midsupply, ac-couple the R_G element to ground through a capacitor. Figure 9-9 shows the midscale buffer driving R_G, thus eliminating the need for an added capacitor. Use a blocking capacitor to move the dc gain to 1 V/V. The voltage on the external, noninverting input of the OPS sets the dc operating point. Use a blocking capacitor to lighten the load on the midscale buffer output and eliminate the bias on R_G when the OPS is disabled.
9. Piezo element drivers operate in a relatively low-frequency range; therefore, the OPS R_F is scaled up even further than the values suggested in Table 8-6. An increased R_F allows R_G to also be scaled up, thereby reducing the load on the midscale buffer, and allow a lower series output resistor to be used into the 220 pF capacitive load.
10. The peak charging current into the capacitive load occurs at the peak dV/dT point. Assuming a 12 MHz sinusoid at 12 V_PP requires a peak output current from the OPS of 6 V_PEAK × 2π × 12 MHz × 220 pF = 100 mA. This result is slightly lesser than the rated minimum peak output current of the OPS.

Using a very low series resistor limits the waveform distortion due to the I × R drop at the peak charging point around the sinusoidal zero crossing. The 100 mA through 5.9 Ω causes a 0.59 V peak drop to the load capacitance around zero crossing. The voltage drop across the series output resistor increases the apparent third harmonic distortion at the capacitive load. Figure 6-45 and Figure 6-46 show 10 V_PP distortion sweeps into various capacitor loads. The results shown in these figures are for the OPS only because the results set the harmonic distortion performance in this example.