SBOS921F December   2018  – November 2023 TMP61

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TMP61 R-T table
      2. 7.3.2 Linear Resistance Curve
      3. 7.3.3 Positive Temperature Coefficient (PTC)
      4. 7.3.4 Built-In Fail Safe
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Thermistor Biasing Circuits
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Thermal Protection With Comparator
          2. 8.2.1.2.2 Thermal Foldback
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Glossary
    5. 9.5 Electrostatic Discharge Caution
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.3 Positive Temperature Coefficient (PTC)

The TMP61 has a positive temperature coefficient. As temperature increases the device resistance increases leading to a reduction in power consumption of the bias circuit. In comparison, a negative coefficient system increases power consumption with temperature as the resistance decreases.

The TMP61 benefits from the reduced power consumption of the bias circuit with less self-heating than a typical NTC system.