SBOS921F December   2018  – November 2023 TMP61

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TMP61 R-T table
      2. 7.3.2 Linear Resistance Curve
      3. 7.3.3 Positive Temperature Coefficient (PTC)
      4. 7.3.4 Built-In Fail Safe
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Thermistor Biasing Circuits
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Thermal Protection With Comparator
          2. 8.2.1.2.2 Thermal Foldback
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Glossary
    5. 9.5 Electrostatic Discharge Caution
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.4 Thermal Information

THERMAL METRIC(1)(2) TMP61 UNIT
DEC (X1SON) LPG (TO-92S) DYA (SOT-5X3)
2 PINS 2 PINS 2 PINS
RθJA Junction-to-ambient thermal resistance(3)(4) 443.4 215 742.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 195.7 99.9 315.8 °C/W
RθJB Junction-to-board thermal resistance 254.6 191.7 506.2 °C/W
ΨJT Junction-to-top characterization parameter 19.9 35.1 109.3 °C/W
YJB Junction-to-board characterization parameter 254.5 191.7 500.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) For information on self-heating and thermal response time see Layout Guidelines section.
(3) The junction to ambient thermal resistance (RθJA ) under natural convection is obtained in a simulation on a JEDEC-standard, High-K board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are included in the PCB, per JESD 51-5.
(4) Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.