SBOS932C January   2020  – March 2021 THP210

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Characterization Configuration
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Super-Beta Input Bipolar Transistors
      2. 8.3.2 Power Down
      3. 8.3.3 Flexible Gain Setting
      4. 8.3.4 Amplifier Overload Power Limit
      5. 8.3.5 Unity Gain Stability
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 I/O Headroom Considerations
      2. 9.1.2 DC Precision Analysis
        1. 9.1.2.1 DC Error Voltage at Room Temperature
        2. 9.1.2.2 DC Error Voltage Over Temperature
      3. 9.1.3 Noise Analysis
      4. 9.1.4 Mismatch of External Feedback Network
      5. 9.1.5 Operating the Power-Down Feature
      6. 9.1.6 Driving Capacitive Loads
      7. 9.1.7 Driving Differential ADCs
        1. 9.1.7.1 RC Filter Selection (Charge Kickback Filter)
        2. 9.1.7.2 Settling Time Driving the ADC Sample-and-Hold Operating Behavior
        3. 9.1.7.3 THD Performance
    2. 9.2 Typical Applications
      1. 9.2.1 MFB Filter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 ADS891x With Single-Ended RC Filter Stage
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Measurement Results
      3. 9.2.3 Attenuation Configuration Drives the ADS8912B
        1. 9.2.3.1 Design Requirements
          1. 9.2.3.1.1 Measurement Results
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Typical Characteristics

at VVS = ±15 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, gain = –1 V/V, and VPD = VVS+ (unless otherwise noted)

GUID-20210224-CA0I-G1KC-PHT1-C2HLTWQLB1ZG-low.png
VS = ±1.5 V, N = 190, mean = –2.66 µV, std dev = 8.81 µV
Figure 6-1 Input Offset Voltage Histogram
GUID-0347B086-D712-4F72-9CAA-85700FDAE2E7-low.gif
VS = ±15 V
Figure 6-3 Input Offset Voltage Drift Histogram
GUID-5BBF7C74-6256-4635-AD51-965FFE8F3A70-low.gif
VS = ±18 V, VOCM = 0 V
Figure 6-5 Output Common Mode Voltage Offset
GUID-74E14862-71C3-430A-8FAC-6607B08FD8B5-low.gif
 
Figure 6-7 Input Bias Current vs Supply Voltage
GUID-4F722BAD-35C5-4AB4-986B-73402183FE97-low.gif
 
Figure 6-9 Current Noise vs Frequency
GUID-5FEEC70C-15D8-48DB-A832-810A4679775A-low.gif
f = 1 kHz, VS = ±15 V
Figure 6-11 Total Harmonic Distortion + Noise vs Amplitude
GUID-05838D32-DCAC-4E35-9012-0D1672B62AA7-low.gif
VS = ±15 V, CL = 50 pF
Figure 6-13 Closed-Loop Gain vs Frequency
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Figure 6-15 Common-Mode Rejection Ratio vs Temperature
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Figure 6-17 Power-Supply Rejection Ratio vs Temperature
GUID-20210317-CA0I-W6CT-FNCV-FSRP2V3FPZBD-low.png
VS = ±15 V
Figure 6-19 Output Impedance vs Frequency
GUID-6199BFD8-4443-4A5D-8F0F-FAF234932005-low.gifFigure 6-21 Quiescent Current vs Temperature
GUID-7D66C13F-A93A-4F42-A0B6-967F76A2CD19-low.gifFigure 6-23 Input Offset Voltage vs
Input Common-Mode Voltage
GUID-12A3135E-28A8-42C7-B2F4-A0422335B835-low.gif
AV = 1
Figure 6-25 Small-Signal Overshoot vs Capacitive Load
GUID-3BF25C78-6FCA-4A5A-81B3-2ED01869B048-low.gifFigure 6-27 Small-Signal Step Response, Falling
GUID-D6E9EE3F-A3AA-4C5E-BC21-CF34292DF281-low.gif
 
Figure 6-29 Output Slew Rate vs Supply Voltage
GUID-326A4E40-843D-431A-8BDC-87309A4B3430-low.gif
 
Figure 6-31 Open-Loop Gain vs Ouput Delta From Supply
GUID-8C69CD67-FDD5-40CC-80E3-C6181424D2F5-low.gifFigure 6-33 Large-Signal Step Response
GUID-440CF2B6-0CFA-4C1B-AF00-94554BFCD1D9-low.gifFigure 6-35 Output Common-Mode Step Response, Falling
GUID-491210D3-2AAA-4C1B-BA46-8697225E516B-low.gifFigure 6-37 Power-Down Time ( PD Low to High)
GUID-AC233A3C-A899-4FA1-B591-EE513C823C67-low.gifFigure 6-39 Output Negative Overload Recovery
GUID-20210224-CA0I-TLF1-STTG-Z37HDX02FPBR-low.svg
VS = ±15 V, N = 120, mean = –1.13 µV, std dev = 5.61 µV
Figure 6-2 Input Offset Voltage Histogram
GUID-0B967274-7B1B-43C4-BF2E-186FAAD90C69-low.gif
VS = ±18 V, VOCM = floating
Figure 6-4 Output Common-Mode Offset Voltage
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Figure 6-6 Input Bias Current vs Input Common-Mode Voltage
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Figure 6-8 Input-Referred Voltage Noise vs Frequency
GUID-C0E0ED4B-E76E-4D24-BE8B-A62D1B30EF41-low.gif
VOUT = 3 VRMS, VS = ±15 V
Figure 6-10 Total Harmonic Distortion + Noise vs Frequency
GUID-3A41A223-B370-4246-9AB2-E37B509DF38E-low.gif
VS = ±15 V, CL = 50 pF
Figure 6-12 Open-Loop Gain vs Frequency
GUID-DD9F7D0B-C71D-4E69-A958-867CD129D47D-low.gif
VS = ±15 V
Figure 6-14 Common-Mode Rejection Ratio vs Frequency
GUID-9EFB1A1E-E25B-43C7-AE4C-A34E185F04BB-low.gif
VS = ±15 V
Figure 6-16 Power-Supply Rejection Ratio vs Frequency
GUID-33308A33-93DE-4689-90A8-46E8E1239E27-low.gif
VS = ±15 V
Figure 6-18 Maximum Output Voltage vs Frequency
GUID-45AB9A69-6DCB-4645-9E18-50C7758FB649-low.gif
 
Figure 6-20 Quiescent Current vs Supply Voltage
GUID-6DCAB923-0C98-4C7E-B80B-D42A5495378E-low.gifFigure 6-22 Quiescent Current vs Power-Down Delta
From Supply Voltage
GUID-643EAEF7-D820-4F23-9CFD-89A8E2360FF6-low.gifFigure 6-24 Output Voltage vs Output Current
GUID-67DA64E3-DCE9-4451-B0D8-95515A5FC84A-low.gif
AV = 10
Figure 6-26 Small-Signal Overshoot vs Capacitive Load
GUID-A07E7C23-5574-437D-A0B8-7DD942A9B8FD-low.gifFigure 6-28 Small-Signal Step Response, Rising
GUID-EAA40BE2-A53C-4124-B99E-A918B7D0686C-low.gif
 
Figure 6-30 Output Voltage vs Output Current
GUID-5BBEF63A-747B-4CCE-984C-C05F7FD53539-low.gif
 
Figure 6-32 Short-Circuit Current vs Temperature
GUID-BC5EEE2F-06C4-43F1-B7E7-319AD907C474-low.gifFigure 6-34 Output Common-Mode Step Response, Rising
GUID-6C2CA388-68EA-46FB-B0F5-B5613228E410-low.gifFigure 6-36 Output Settling Time to ±0.01%
GUID-D8008BC9-A808-4354-8C8F-5E54B6BA0643-low.gifFigure 6-38 Power-Down Time ( PD High to Low)
GUID-7E0C60A7-3CB8-411A-9638-5F9EC43267B8-low.gifFigure 6-40 Output Positive Overload Recovery