SBOS932C January   2020  – March 2021 THP210

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Characterization Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Super-Beta Input Bipolar Transistors
      2. 8.3.2 Power Down
      3. 8.3.3 Flexible Gain Setting
      4. 8.3.4 Amplifier Overload Power Limit
      5. 8.3.5 Unity Gain Stability
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 I/O Headroom Considerations
      2. 9.1.2 DC Precision Analysis
        1. 9.1.2.1 DC Error Voltage at Room Temperature
        2. 9.1.2.2 DC Error Voltage Over Temperature
      3. 9.1.3 Noise Analysis
      4. 9.1.4 Mismatch of External Feedback Network
      5. 9.1.5 Operating the Power-Down Feature
      6. 9.1.6 Driving Capacitive Loads
      7. 9.1.7 Driving Differential ADCs
        1. 9.1.7.1 RC Filter Selection (Charge Kickback Filter)
        2. 9.1.7.2 Settling Time Driving the ADC Sample-and-Hold Operating Behavior
        3. 9.1.7.3 THD Performance
    2. 9.2 Typical Applications
      1. 9.2.1 MFB Filter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 ADS891x With Single-Ended RC Filter Stage
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Measurement Results
      3. 9.2.3 Attenuation Configuration Drives the ADS8912B
        1. 9.2.3.1 Design Requirements
          1. 9.2.3.1.1 Measurement Results
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

9.1.3 Noise Analysis

An accurate output-noise calculation allows the designer to compare the performance of alternate FDA solutions. The combination of differential spot noise at the output pins of the FDA with any passive filtering to the ADC enables an accurate signal-to-noise ratio (SNR) calculation. This chapter incorporates key elements for an output noise analysis.

The first step in the output noise analysis is to reduce the application circuit to the simplest form with equal feedback and gain setting elements to ground. Figure 9-4 shows the simplest analysis circuit with the FDA. This circuit considers the thermal resistor noise terms of the external feedback network and the intrinsic input voltage and current noise terms.

GUID-EB4E344C-CF10-40AC-B687-48276553A992-low.gif Figure 9-4 FDA Noise Analysis Circuit

The noise powers are shown in Figure 9-4 for each term. When the RF and RG (or RI) terms are matched on each side, the total differential output noise is the root sum squared (RSS) of these separate terms.

Using NG ≡ 1 + RF / RG as the noise gain, the total output noise density is given by Equation 3. Each resistor noise term is a 4kT × R power (4kT = 1.6E-20 J at 290 K).

Equation 3. GUID-EF30D6E2-BF6E-4FA1-ACBF-A3B2D4C807E3-low.gif

where:

  • eni is the differential input spot noise times the noise gain.
  • in x RF is the input current noise terms times the feedback resistor.
    Because there are two uncorrelated current noise terms, the power is two times one of them.
  • enRF is the thermal output noise resulting from both the RF and RG resistors at twice the value for the output noise power of each side added together.

Figure 9-5 and Figure 9-6 provide a graphical comparison of the described noise densities versus different gain settings. Each of the contributors are separately showcased in the graphs. As expected, lower feedback resistors (in this case, 2 kΩ) show that the dominant factor of the total output noise is the intrinsic voltage noise of the FDA (at gains > 2). For smaller gain settings, the thermal noise of the feedback resistors is dominating.

GUID-929F1584-F454-4A36-A4E2-4B2B39149CE1-low.gif
RF = 2 kΩ
Figure 9-5 Calculated Noise Densities
vs Gain Settings
GUID-BE6FEC7D-2677-4BC9-A728-30005081E094-low.gif
RF = 10 kΩ
Figure 9-6 Calculated Noise Densities
vs Gain Settings

The advancement of the THP210 can be seen at higher feedback resistors (in this case 10 kΩ). Many FDAs exhibit an input current noise density in the range of some pA/√Hz that, in cases for higher feedback resistors, dictate the noise behavior. As a result of the superior current noise density of 300 fA/√Hz of the THP210, the overall output noise is mainly dominated by the thermal noise of the resistors (here, up to gains of approximately 15).

The total output voltage noise density is important when using FDAs as ADC input driver stages. To evaluate the compatibility between the input driver and the ADC from a noise perspective, compare the calculated RMS output noise of the FDA with the least-significant bit (LSB) of the desired ADC application, in respect to the effective number of bits (ENOB). Section 9.2.2 shows measurements of the THP210 in combination with state-of-the-art SAR ADCs, and indicates the performance that is achieved.