SBOS974E August   2019  – October 2024 THS6222

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics VS = 12 V
    6. 5.6 Electrical Characteristics VS = 32 V
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics: VS = 12 V
    9. 5.9 Typical Characteristics: VS = 32 V
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Common-Mode Buffer
      2. 6.3.2 Thermal Protection and Package Power Dissipation
      3. 6.3.3 Output Voltage and Current Drive
      4. 6.3.4 Breakdown Supply Voltage
      5. 6.3.5 Surge Test Results
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Broadband PLC Line Driving
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Best Design Practices
      1. 7.3.1 Do
      2. 7.3.2 Do Not
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Wafer and Die Information
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.6 Electrical Characteristics VS = 32 V

at TA ≈ 25°C, differential closed-loop gain (AV) = 10 V/V, differential load (RL) = 100 Ω, RF = 1.24 kΩ, RADJ = 0 Ω, VCM = open, VO = D1_OUT – D2_OUT, and full bias (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth, –3 dB AV = 5 V/V, RF = 1.5 kΩ, VO = 2 VPP 285 MHz
AV = 10 V/V, RF = 1.24 kΩ, VO = 2 VPP 205
0.1-dB bandwidth flatness 13 MHz
LSBW Large-signal bandwidth VO = 40 VPP 170 MHz
SR Slew rate (20% to 80% level) VO = 40-V step 11,000 V/µs
Rise and fall time VO = 2 VPP 2 ns
HD2 2nd-order harmonic distortion AV = 10 V/V,
VO = 2 VPP,
RL = 100 Ω		 Full bias, f = 1 MHz –86 dBc
Low bias, f = 1 MHz –79
Full bias, f = 10 MHz –71
Low bias, f = 10 MHz –63
HD3 3rd-order harmonic distortion AV = 10 V/V,
VO = 2 VPP,
RL = 100 Ω		 Full bias, f = 1 MHz –101 dBc
Low bias, f = 1 MHz –88
Full bias, f = 10 MHz –80
Low bias, f = 10 MHz –65
en Differential input voltage noise f ≥ 1 MHz, input-referred 2.5 nV/√Hz
in+ Noninverting input current noise (each amplifier) f ≥ 1 MHz 1.7 pA/√Hz
in- Inverting input current noise (each amplifier) f ≥ 1 MHz 18 pA/√Hz
DC PERFORMANCE
ZOL Open-loop transimpedance gain 1500 kΩ
Input offset voltage ±12 mV
Input offset voltage drift TA = –40°C to +85°C –40 µV/°C
Input offset voltage matching Amplifier A to B ±0.5 mV
Noninverting input bias current ±1 µA
Inverting input bias current ±6 µA
Inverting input bias current matching ±8 µA
INPUT CHARACTERISTICS
Common-mode input voltage Each input ±11 ±12 V
CMRR Common-mode rejection ratio Each input 53 65 dB
Noninverting input resistance 10 || 2 kΩ || pF
Inverting input resistance 38 Ω
COMMON-MODE BUFFER CHARACTERISTICS
VCM-OS Common-mode offset voltage Voltage at VCM with respect to
midsupply		 ±3.9 mV
Common-mode voltage noise With and without 100-nF VCM noise-decoupling capacitor, f ≥ 50 kHz 21 nV/√Hz
Common-mode output resistance f = DC 520 Ω
OUTPUT CHARACTERISTICS
VO Output voltage swing(1) RL = 100 Ω ±28.5 V
RL = 25 Ω ±16.3
IO Output current (sourcing and sinking)(1) RL = 25 Ω, based on VO specification ±580 ±665 mA
Short-circuit output current 1 A
ZO Output impedance f = 1 MHz, differential 0.01 Ω
POWER SUPPLY
IS+ Quiescent current Full bias (BIAS-1 = 0, BIAS-2 = 0) 23 mA
Mid bias (BIAS-1 = 1, BIAS-2 = 0) 17.7
Low bias (BIAS-1 = 0, BIAS-2 = 1) 12.2
Bias off (BIAS-1 = 1, BIAS-2 = 1) 1.5 1.8
IS– Quiescent current Full bias (BIAS-1 = 0, BIAS-2 = 0) 22 mA
Mid bias (BIAS-1 = 1, BIAS-2 = 0) 16.7
Low bias (BIAS-1 = 0, BIAS-2 = 1) 11.2
Bias off (BIAS-1 = 1, BIAS-2 = 1) 0.5 0.8
Current through GND pin Full bias (BIAS-1 = 0, BIAS-2 = 0) 1 mA
+PSRR Positive power-supply rejection ratio Differential 83 dB
–PSRR Negative power-supply rejection ratio Differential 77 dB
BIAS CONTROL
Bias control pin voltage With respect to DGND,
TA = –40°C to +85°C		 0 3.3 16.5 V
Bias control pin logic threshold Logic 1, with respect to DGND,
TA = –40°C to +85°C		 1.9 V
Logic 0, with respect to DGND,
TA = –40°C to +85°C		 0.8
Bias control pin current(2) BIAS-1, BIAS-2 = 0.5 V (logic 0) –15 –10 µA
BIAS-1, BIAS-2 = 3.3 V (logic 1) 0.1 1
(1) See Output Voltage and Current Drive and Figure 5-51 for output voltage vs output current characteristics.
(2) Current is considered positive out of the pin.