SBOSAA9A March   2023  – June 2024 TRF0208-SEP

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Fully-Differential Amplifier
      2. 6.3.2 Single Supply Operation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Down Mode
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a High-Speed ADC
      2. 7.1.2 Calculating Output Voltage Swing
      3. 7.1.3 Thermal Considerations
    2. 7.2 Typical Applications
      1. 7.2.1 TRF0208-SEP in Receive Chain
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Mechanical Data

Electrical Characteristics

at TA = 25°C, VDD = 3.3V, 50Ω single-ended input, and 100Ω differential output (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal 3dB bandwidth VO = 0.1VPP 11 GHz
LSBW Large-signal 3dB bandwidth VO = 1VPP 11 GHz
1dB BW Bandwidth for 1dB flatness 8 GHz
S21 Power gain f = 2GHz 16 dB
S11 Input return loss f = 10MHz to 8GHz –10 dB
S12 Reverse isolation f = 2GHz –35 dB
ImbGAIN Gain imbalance f = 10MHz to 8GHz ± 0.3 dB
ImbPHASE Phase imbalance f = 10MHz to 8GHz ± 3 degrees
CMRR Common-mode rejection ratio(1) f = 2GHz –45 dB
HD2 Second-order harmonic distortion f = 0.5GHz, PO = 3dBm –70 dBc
f = 2GHz, PO = 3dBm –65
f = 6GHz, PO = 3dBm –52
f = 8GHz, PO = 3dBm –50
HD3 Third-order harmonic distortion f = 0.5GHz, PO = 3dBm –68 dBc
f = 2GHz, PO = 3dBm –63
f = 6GHz, PO = 3dBm –54
f = 8GHz, PO = 3dBm –60
IMD2 Second-order intermodulation distortion f = 0.5GHz, PO =  –4dBm per tone
(10MHz spacing)
–72 dBc
f = 2GHz, PO =  –4dBm per tone
(10MHz spacing)
–64
f = 6GHz, PO =  –4dBm per tone
(10MHz spacing)
–54
f = 8GHz, PO =  –4dBm per tone
(10MHz spacing)
–48
IMD3 Third-order intermodulation distortion f = 0.5GHz, PO =  –4dBm per tone
(10MHz spacing)
–77 dBc
f = 2GHz, PO =  –4dBm per tone
(10MHz spacing)
–80
f = 6GHz, PO =  –4dBm per tone
(10MHz spacing)
–70
f = 8GHz, PO =  –4dBm per tone
(10MHz spacing)
–48
OP1dB Output 1dB compression point f = 0.5GHz 11 dBm
f = 2GHz 14.5
f = 6GHz 11
f = 8GHz 7.5
OIP2 Output second-order intercept point f = 0.5GHz, Po = –4dBm per tone
(10MHz spacing)
68 dBm
f = 2GHz, Po = –4dBm per tone
(10MHz spacing)
60
f = 6GHz, Po = –4dBm per tone
(10MHz spacing)
50
f = 8GHz, Po = –4dBm per tone
(10MHz spacing)
45
OIP3 Output third-order intercept point f = 0.5GHz, Po = –4dBm per tone
(10MHz spacing)
34 dBm
f = 2GHz, Po = –4dBm per tone
(10MHz spacing)
36
f = 4GHz, Po = –4dBm per tone
(10MHz spacing)
35
f = 6GHz, Po = –4dBm per tone
(10MHz spacing)
32
f = 8GHz, Po = –4dBm per tone
(10MHz spacing)
21
NF Noise Figure f = 0.5GHz 6.5 dB
f = 2GHz 6.8
f = 6GHz 6.8
f = 8GHz 8.5
IMPEDANCE
ZO-DIFF Differential output impedance f = dc (internal to the device) 3 Ω
ZIN Single-ended input impedance INM pin terminated with 50Ω 50 Ω
TRANSIENT
VOMAX Maximum output voltage (differential) 2 VPP
VOSAT Output saturated voltage level (differential) f = 2GHz 3.9 VPP
tREC Overdrive recovery time Using a –0.5VP input pulse of 2ns duration 0.2 ns
POWER SUPPLY
IQA Active current Current on VDD pin, PD = 0 138 mA
IQPD Power-down quiescent current Current on VDD pin, PD = 1 7 mA
ENABLE
VPDHIGH PD pin logic high 1.45 V
VPDLOW PD pin logic low 0.8 V
IPDBIAS PD bias current (current on PD pin) PD = high (1.8V logic) 50 100 µA
PD = high (3.3V logic) 200 250
CPD PD pin capacitance 2 pF
tON Turn-on time 50% VPD to 90% RF 200 ns
tOFF Turn-off time 50% VPD to 10% RF 50 ns
Calculated using the formula (S21 – S31) / (S21 + S31). Port-1: INP, Port-2: OUTP, Port-3: OUTM.